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IGEP

Hardware Reference Manual

™

is a registered trademar k from ISEE 2007 S.L. The followi ng is provided for informational purpos es onl y.

DOCUMENT FROM ISEE 2007 S.L. Ref: MAN-PR-IGEP0020-RCx

Table of contents

Table of contents .................................................................................................................2

WARRANTY ...............................................................................................................4

ORDERING INFORMATION .........................................................................................5

OVERVIEW ................................................................................................................6

4.1

ABOUT THIS MANUAL ............................................................................................6

4.2

IGEP

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v2 DESCRIPTION ...........................................................................................6

4.3

IGEP

v2 FEATURES ..............................................................................................8

4.4

IGEP

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v2 BLOCK DIAGRAM ...................................................................................11

4.5

GENERAL VIEW ....................................................................................................12

ON-BOARD DEVICES & INTERFACES ..........................................................................14

5.1

SUMMARY ..........................................................................................................14

5.2

IGEP

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v2 CONNECTORS MAP ................................................................................15

5.3

OMAP PROCESSOR ..............................................................................................16

5.4

MEMORY ............................................................................................................16

5.5

POWER MANAGEMENT .......................................................................................16

5.6

WIFI/BLUETOOTH INTERFACE ...............................................................................17

5.6.1

BLOCK DIAGRAM ..........................................................................................17

5.6.2

INTERFACES .................................................................................................17

5.6.3

POWER-ON RESET SEQUENCE FOR WLAN ......................................................18

5.6.4

WLAN RESET/PDN PINS.................................................................................19

5.6.5

BLUETOOTH RESET PINS ...............................................................................19

5.6.6

PCM INTERFACE ...........................................................................................20

5.6.7

IGEP

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v2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22) .....................20

5.7

MAIN 5Vdc POWER: J200 ....................................................................................24

5.8

JTAG DEBUG: J400 ..............................................................................................24

5.9

RS485: J940 ........................................................................................................26

5.10 SERIAL PORT DEBUG (+ EXTRA RS232) J960 ...........................................................28

5.10.1

DEBUG CABLE MODIFICATIONS (ONLY REV C) ................................................29

5.10.2

NEW FEATURES ON REV C .............................................................................30

5.10.3

HOW TO USE UART 1 ....................................................................................31

5.11 KEYBOARD MATRIX 4x4: J970 ...............................................................................32

5.12 TFT INTERFACE CONNECTORS: JA41 & JA42...........................................................34

Содержание IGEP v2

Страница 1: ...Document MAN PR IGEP0020 RCx Revision 2 0 Date February 6 2013 IGEP TM v2 HARDWARE REFERENCE MANUAL ...

Страница 2: ... DEVICES INTERFACES 14 5 1 SUMMARY 14 5 2 IGEP v2 CONNECTORS MAP 15 5 3 OMAP PROCESSOR 16 5 4 MEMORY 16 5 5 POWER MANAGEMENT 16 5 6 WIFI BLUETOOTH INTERFACE 17 5 6 1 BLOCK DIAGRAM 17 5 6 2 INTERFACES 17 5 6 3 POWER ON RESET SEQUENCE FOR WLAN 18 5 6 4 WLAN RESET PDN PINS 19 5 6 5 BLUETOOTH RESET PINS 19 5 6 6 PCMINTERFACE 20 5 6 7 IGEP v2 ANTENNAS INTERNAL EXTERNAL UD11 JD21 JD22 20 5 7 MAIN 5Vdc P...

Страница 3: ...ACE JC30 41 5 15 S VIDEO SIGNALS TP400 TP401 43 5 16 RTC BACKUP BATTERY 44 5 17 USB 2 0 OTG J830 47 5 18 USB 2 0 HOST J800 48 5 19 ETHERNET JB01 49 5 20 AUDIO J650 J640 50 5 21 DVI D INTERFACE JA01 53 5 22 MICRO SD J900 54 5 23 LED INDICATORS D240 D440 54 6 EXPANSION CONNECTOR J990 GPIO 55 6 1 PINOUT TABLE OF EXPANSION CONNECTOR 58 7 EXPANDING IGEP v2 CAPABILITIES 59 7 1 IGEP v2 EXPANSION BOARD 59...

Страница 4: ...handling of the goods Further the user indemnifies ISEE 2007 SL from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT S...

Страница 5: ...ed trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 5 3 ORDERING INFORMATION IGEP Device Orderable PN Marking IGEP v2 IGEP0020 RCx Datamatrix code label with IGEP0020 RCx Table 1 Orderinginformation ...

Страница 6: ...ector included on the board 8 MECHANICAL SPECIFICATIONS chapter describes the mechanical characteristics of the product and finally chapter 9 ELECTRICAL CHARACTERISTICS show a table with the electrical specifications of the product At the end of this document you will find a list of tables figures and change log You will find these elements in chapters 10 LIST OF TABLES 11 LIST OF FIGURES 12 KNOWN...

Страница 7: ...50 Super Capacitor or Rechargeable Battery Optional 3Msps ADC LED Indicators Size 93x64mm Non populated parts o J400 JTAG connector o J990 GPIO expansion connector o J970 4x4 keyboard connector o JD22 External wifi antenna connector o JA41 and JA42 TFT interface o JC30 Camera interface o UC20 3MBps ADC JC21 Hirose connector o Super Capacitor or Rechargeable Battery Contact ISEE sales for custom as...

Страница 8: ...KB ARM L2 cache 96 KB DSP 256 KB ARM NEON SIMD Coprocessor DMA Interrupt controllers Timers DSP TMS320DM C64 500 Mhz 800 Mhz 2D 3D graphics acceleration Power VR SGX 530 100 200 Mhz providing 2D 3D graphics acceleration with OpenGL ES 1 0 OpenGL ES 2 0 and OpenVG support Video acceleration IVA2 2 Subsystem TMS320C64 DSP core running at rate up to 520MHz Supporting H 264 H 263 MPEG 4 MPEG 2 JPEG WM...

Страница 9: ...ector dual slave and host role USB 2 0 HS HOST 1 Type A USB socket connector standard USB host Audio stereo in out 3 5mm standard stereo audio jack microSD microSD connector SD and SDHC cards supported DVI video output DVI D using HDMI connector video and TS lines are available in expansion connector also Ethernet 10 100 MB BaseT RJ45 connector with led link activity Expansion connector Power 5V a...

Страница 10: ...5Vcc 1 3A With USB 3 5mm socket connector for wall plug or JST Connector Power fromexpansion connectors Supply Voltage from 5V and 1 8V Power Management TPS65950 Table 6 Power Feature Specifications Temperature Range Commercial 0 to 70 Cº and Industrial range 40 to 85 Cº Degrees are available Contact ISEE sales PCB size 93 x 64 x 1 6 mm Table 7 Mechanical andenvironmental WARNING IGEP v2 BOARD CAN...

Страница 11: ...All rights reserved IGEP is a registered trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 11 4 4 IGEP v2 BLOCK DIAGRAM Figure 3 IGEP v2 revision C Block Diagram ...

Страница 12: ...l rights reserved IGEP is a registered trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 12 4 5 GENERAL VIEW Figure 4 IGEP v2 revision C board top side components ...

Страница 13: ... S L All rights reserved IGEP is a registered trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 13 Figure 5 IGEP v2 revision C board bottom side components ...

Страница 14: ...SCEIVER SERIAL DEBUG HEADER 2x5 2 54mm pitch J960 UART3 UART1 TRANSCEIVER KEYBOARD MATRIX 8 pin 2 54mm pitch J970 Keyboard matrix4x4 TFT INTERFACE 2x14pin 1 27mm pitch JA41 DSS_DATA0 23 TFT INTERFACE II 2x10pin 1 27mm pitch JA42 LCD SYNC TOUCHSCREEN ETC ANALOG to DIGITAL CONVERTER JC20 U FL R SMT 1 JC21 2pin 2 54mm pitch JC20 JC21 OPTIONAL ANALOG INPUT TO ADC CAMERA INTERFACE 2x14pin 1 27mm pitch ...

Страница 15: ...ll rights reserved IGEP is a registered trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 15 5 2 IGEP v2 CONNECTORS MAP Figure 6 IGEP v2 revision C CONNECTORS MAP ...

Страница 16: ...you will notfind an actual part labeled OMAP3530 or DM3730 Figure 7 POP Package For accurate information on this processor revise OMAP DATA MANUAL official document from Texas Instruments official site http focus ti com 5 4 MEMORY The memory is mounted on top of the processor as mentioned The key function of the POP memory is to provide 4Gb Giga Bits NAND x 16 512 Mega Bytes 4Gb Giga Bits LP DDR S...

Страница 17: ...ROM 21e Bluetooth 2 0 compliant Class 2 2 5 mW 4 dBm 10 meters Version 2 0 EDR 3 Mbit s 5 6 1 BLOCK DIAGRAM Figure 8 Wi Fi Bluetooth Combo module block Diagram 5 6 2 INTERFACES Terminal Name Type System Description RST_N_B I BT Reset activelow It must be low for 5ms PCM_OUT O BT Synchronous data output CMOS output tri statable with weak internal pull down PCM_SYNC I O BT Synchronous data sync BiDi...

Страница 18: ...p Select input SDIO4 bit Mode SD_DAT 0 Data Line Bit 0 SDIO 1 bit Mode SD_DAT 0 Data Line SDIO SPI Model SD_DAT 0 Data Output SD_CMD SPI_SDI I O WLAN G SPI Mode SPI_SDI G SPI Data Input SDIO 4 bit Mode SD_CMD Command Response SDIO 1 bit Mode SD_CMD CommandLine SDIO SPI Model SD_CMD Data Input SD_CLK SPI_CLK I O WLAN G SPI Mode SPI_CLK G SPI Clock Input SDIO 4 bit Mode SD_CLK Clock Input SDIO 1 bit...

Страница 19: ...ls pulsing of RESET_N_W pin 5 6 4 WLAN RESET PDN PINS Reset can be done by using GPIO_94 or GPIO_138 See your IGEP v2 model to know default assembly option See FAQ in http labs igep es Power down can be done by using GPIO_95 or GPIO_139 See your IGEP v2 model to know default assembly option See FAQ in http labs igep es 5 6 5 BLUETOOTH RESET PINS Reset can be done by using GPIO_182 or GPIO_137 See ...

Страница 20: ... internal pull down PCM_SYNC I O Synchronous data sync Bi Directional with weak internal pull down PCM_IN Input Synchronous data input CMOS input with weak pull down PCM_CLK I O Synchronous data clock Bi Directional with weak internal pull down McBSP3 it s connected to OMAP3530 DM3730 and TPS65950 PCMVSP 5 6 7 IGEP v2 ANTENNAS INTERNAL EXTERNAL UD11 JD21 JD22 For the cable you will find cable asse...

Страница 21: ...EE 2007 S L Ref MAN PR IGEP0020 RCx 21 Figure 9 U FL series receptacle connector specification Figure 10 U FL series Mated connector PERMANENT DAMAGE CAN BE CAUSED IF ANY VOLTAGE IS APPLIED TO JD21 AND JD22 CONNECTORS ENSURE CORRECT INSERTION ON COAXIAL CONNECTOR IN ORDER TO DO NOT LOSE RF PERFORMANCE There are several ways to configure wifi bluetooth antennas for IGEP v2 revision C board series ...

Страница 22: ...a layout OPTION 1 An internal shared antenna for both BT and WIFI interfaces This is default factory configuration for IGEP v2 revision C UD11 LD30 1 8nH LD31 1 5nH CD31 15pF are populated JD21 JD22 CD32 and CD33 are not populated OPTION 2 An external shared antenna for both BT and WIFI interfaces JD22 is populated JD21 UD11 LD30 LD31 CD31 CD32 and CD33 are not populated NOTE Contact ISEE sales fo...

Страница 23: ...tered trademar kfrom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 23 Figure 13 IGEP v2 revision C JD21 JD22 location JD22 on yellow box up JD21 on blue box down Figure 14 IGEP v2 revision C JD21 JD22 detail ...

Страница 24: ...5 5mm OD or any other compatible J940 can also be used to power the board please refer to this connector section 5 9 RS485 IGEP v2 MUST BE POWERED THROUGH J200 or J940 ONLY WITH 5Vdc PERMANENT DAMAGE IF ANY OTHER VOLTAGE IS APPLIED ENSURE TOTAL CURRENT DRAIN IS LOWER THAN 1A DO NOT POWER WITH THE TWO CONNECTORS AT THE SAME TIME USE ONLY ONE OF THEM 5 8 JTAG DEBUG J400 A 14 pin JTAG header is provi...

Страница 25: ...l Pins 1 2 13 and 14 are labeled on the PCB The connector islocated as shows the figure below Figure 17 J400 location The schematic belowillustrate the pin out of the connector Figure 18 Schematic J400 WARNING JTAG signals go directly to OMAP processor Improper use of this connector could result in permanent damage of the processor ISEE Suggested JTAG a ISEE recommend JTAG Debugger XDS510 USB from...

Страница 26: ...er Studio 4 or higher 5 9 RS485 J940 The J940 connector is a HEADER CONNECTOR PH SIDE 5POS 2MM SMD from JST Part Number S5B PH SM3 TB It matches to JST CONNECTOR HOUSING PH 5POS 2MM WHITE Part Number JST PHR 5 and JST TERMINALS CRIMP PH 24 30AWG Part Number JST SPH 002T P0 5S IGEP v2 don t include cable neither plug connector Pin 1 is labeled on the PCB The connectoris located as shownin the figur...

Страница 27: ...power the board with 5VDC Use only 5V regulated DC IGEP v2 BOARD does not use this 9v power supply Only on IGEP v2 revision B the PWR_9V input is directly routed to JC01 and J970 connectors On IGEP v2 revision C is not available There is also a RS485 transceiver on the connector Figure 22 Schematic RS485 driver Figure 23 Schematic level shifters for RS485 driver Contact ISEE sales for custom assem...

Страница 28: ...nnector is a 5x2 pins double row 2 54mm Figure 24 J960 detail The connector islocated as showed in the figure below Figure 25 J960 location Figure 26 IDC 10 to DB9 cable The 5x2 Headerfollow the IDC 10 AT Everex configuration So it is needed null modem configuration connection between two computers RX and TX lines are crossedin this null modem configuration between two equipments TX1 RX2 TX2 RX1 T...

Страница 29: ...SCEIVER ON IGEPTM v2 BOARD REVISION C YOU MAY NEED TO MODIFY YOUR SERIAL DEBUG CABLE IN ORDER TO AVOID POSSIBLE MALFUNCTIONNING 5 10 1 DEBUG CABLE MODIFICATIONS ONLY REV C Only on IGEPTM v2 BOARD REVISION C you may require to make some modifications ONLY in case you connect your IGEPTM v2 with an old device that needs RTS and or RTC signals Due to some pins of J960 connector are connected to groun...

Страница 30: ...nal RS232 port UART1 on same J960 connector It is only needed to rotate 180º the IDC 10 AT Everex to DB9 cable It has been added resistors for alternative UART1 UART2 and UART3 hardware selection Also IGEP v2 revision C series have debug RS232 interface with transceiver UART3 like IGEP v2 revision B series The schematic belowillustrate IGEP v2 revision C pin out of the connector Figure 28 IGEP v2 ...

Страница 31: ... RS485 you need configure to UART1_RTS and UART1_CTS pins in safe mode To do that you have two options 1 Modify your kernel a On file board igep0020 c b On function static void __init igep2_init void c After line omap3_mux_init board_mux OMAP_PACKAGE_CBB d Place this two lines i omap_mux_init_signal uart1_rts safe_mode 0 ii omap_mux_init_signal uart1_cts safe_mode 0 2 From kernel space a mount t d...

Страница 32: ...OCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 32 5 11 KEYBOARD MATRIX 4x4 J970 The J970 connector is an 8 pins single row 2 54mm It is not populated by default on IGEP v2 boards Figure 30 J970 detail It can be used to connect a 4x4 keyboard matrix Figure 31 Keyboard matrix 4x4 and schematic example Pin 1 is labeled on the PCB The connectoris located as shows the figure below ...

Страница 33: ...ustrate the pin out of the connector Figure 33 Schematic J971 KPD_Cx columns KPD_Rx rows When a key button of the keyboard matrix is pressed the corresponding row and column lines are shorted together To allow key press detection all input pins KBR are pulled up to VCC and all output pins KBC driven to a low level Any action on a button generates an interrupt to the sequencer The decoding sequence...

Страница 34: ... ISEE 2007 S L Ref MAN PR IGEP0020 RCx 34 5 12 TFT INTERFACE CONNECTORS JA41 JA42 There are two 1 27mm Double Row Terminal Strip for the TFT interface Both are from SAMTEC manufacturer PartNumber FTS 114 01 L D FTS 110 01 L D 5 12 1 CONNECTOR JA41 Figure 34 IGEP v2 revision C JA41 location Figure 35 IGEP v2 revision C JA41 and JA42 detail Figure 36 IGEP v2 revision C JA41 JA42 pin out detail ...

Страница 35: ...E0 MODE2 MODE3 MODE4 MODE5 MODE7 JA41 1 PWR 3V3 JA41 2 PWR GND JA41 3 OMAP dss_data0 DVI_DATA0 uart1_cts dssvenc656_d0 gpio_70 safe_mode JA41 4 OMAP dss_data1 DVI_DATA1 uart1_rts dssvenc656_d1 gpio_71 safe_mode JA41 5 OMAP dss_data2 DVI_DATA2 dssvenc656_d2 gpio_72 safe_mode JA41 6 OMAP dss_data3 DVI_DATA3 dssvenc656_d3 gpio_73 safe_mode JA41 7 OMAP dss_data4 DVI_DATA4 uart3_rx_irrx dssvenc656_d4 g...

Страница 36: ...8 OMAP I2C3_SDA gpio_185 safe_mode Table 11 JA41 Connector signals The schematic belowillustrates the pin out of the connector Figure 37 IGEP v2 rev C Schematic of JA41 connector All IGEP v2 boards Revisions B and C are mechanical electrical and logical compatible This allows for the creation of LCD boards to support different LCD panels Be aware all OMAP type pins are 1V8 level If you need to wor...

Страница 37: ...cmd gpio_175 safe_mode JA42 13 OMAP mcbsp4_dx LCD_QVGA nVGA gpio_154 hsusb3_tll_d2mm3_txdat safe_mode JA42 14 OMAP mcbsp4_dr LCD_ENVDD gpio_153 hsusb3_tll_d0mm3_rxrcv safe_mode JA42 15 OMAP mcbsp4_fsx LCD_RESB gpio_155 hsusb3_tll_d3mm3_txennsafe_mode JA42 16 OMAP mcbsp4_clkx LCD_INI gpio_152 hsusb3_tll_d1mm3_txse0safe_mode JA42 17 OMAP MCSPI1_CLK mmc2_d4 gpio_171 safe_mode JA42 18 OMAP MCSPI1_SIMO...

Страница 38: ...er When High DVIis enabled Can be used to activate circuitry on adapter board if desired NOTE JA41 and JA42 connectors are NOT Beagle Board compatible WARNING TFT signals go directly to OMAP processor Improper use of this connector could result on permanent damage to this processor 5 12 3 CONNECTORs JA41 JA42COUNTERPARTs JA41 and JA42 mates with SFMC SAMTEC Series Figure 40 IGEP v2 revision C JA41...

Страница 39: ... is a U FL series HIROSE connector to input analog signals to the analog to digital converter Connector Part number is U FL R SMT 1 or any other compatible There is also connector JC21 2pin 2 54mm pitch Header in parallel for this feature On IGEP v2 Revision C analog to digital converter device JC20 and JC21 are not populated by default Contact ISEE sales for custom assembly boardsfor this feature...

Страница 40: ... The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 40 Several ADC devices can be populated For example ADC SPI 3MSps 3V3 LTC2366 ADC SPI 1MSps 5VDC ADC121S101 Figure 43 IGEP v2 revision C schematic A D Figure 44 IGEP v2 revision C schematic A D SPI interface ...

Страница 41: ...020 RCx 41 5 14 CAMERA INTERFACE JC30 There is one 1 27mm Double Row Terminal Strip for the Camera interface from SAMTEC manufacturer Part Number FTS 114 01 L D This JC30 connector is only available on IGEP v2 revision C series Figure 45 IGEP v2 revision C JC30 location Figure 46 IGEP v2 revision C JC30 detail Figure 47 IGEP v2 revision C JC30 pin out detail These connectors allow the access to th...

Страница 42: ...0 MODE2 MODE4 MODE5 MODE7 JC30 1 OMAP CAM_HS Power Down WiFi gpio_94 hw_dbg0 safe_mode JC30 2 OMAP CAM_VS Reset WiFi gpio_95 hw_dbg1 safe_mode JC30 3 OMAP CAM_XCLKA gpio_96 safe_mode JC30 4 PWR GND JC30 5 OMAP CAM_PCLK gpio_97 hw_dbg2 safe_mode JC30 6 PWR GND JC30 7 OMAP CAM_D0 gpio_99 safe_mode JC30 8 OMAP CAM_FLD cam_global_rst gpio_98 hw_dbg3 safe_mode JC30 9 OMAP CAM_D2 gpio_101 hw_dbg4 safe_m...

Страница 43: ...s suggested that the 3V3 rail be used to generate the required voltages for an adapter card The schematic below illustrate the pin out of the connectors Figure 48 IGEP v2 revision C JC30 schematic WARNING CAMERA signals go directly to OMAP processor Improper use of this connector could result on permanent damage to this processor 5 15 S VIDEO SIGNALS TP400 TP401 S video signals are available on TP...

Страница 44: ...rocessor 5 16 RTC BACKUP BATTERY The TPS65950 implements a backup mode in which the backup battery keeps the RTC running A rechargeable backup battery can be recharged from the main battery This RTC feature is only available on IGEP v2 revision C series When the main battery is below 2 7 V or is removed the backup battery powers the backup if the backup battery voltage is greater than 1 8 V The ba...

Страница 45: ...EE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 45 BT741 is Lithium Coin Battery VL Series from Panasonic Figure 52 BT741 specification C741 is an Electric Double Layer Capacitors from PANASONIC EN Series Figure 53 C741 specification ...

Страница 46: ...rom ISEE 2007 S L The followi ng is provided for informational purposes onl y DOCUMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 46 Figure 54 IGEP v2 revision C BT741 location Figure 55 IGEP v2 revision C C741 location ATTENTION If battery is needed resistor R741 MUST BE REMOVED Figure 56 R741 location ...

Страница 47: ...munications Complies with the USB 2 0 standard for high speed 480 Mbps function and with on the go OTG supplement Supports USB 2 0 peripheral at High Speed 480 Mbps and Full Speed 12 Mbps Supports USB 2 0 host at High 480 Mbps Full 12 Mbps and Low Speed 1 5 Mbps J830 is an USB Type mini AB Socket Connector with Part Number FCI 10033527 N3212MLF or any other compatible The USB OTG signals are avail...

Страница 48: ...hen using USB power is mandatory you check the maximum current consumptionis lower than 500mA USB HOST Port supports only high speed devices USB 2 0 HS devices In order to support low speed devices USB 1 0 LS devices or full speed devices USB 1 1 FS devices external self powered USB 2 0 HUB must be used J800 is RECEPTACLE USB TYPE A CONNECTOR with Part Number ASSMAN USB 1A or any other compatible ...

Страница 49: ... by a High Performance 16 bit Non PCI 10 100 Ethernet Controller with Variable Voltage I O for each of the ports implemented with the SMSC LAN9221i There is an optional EEPROM memory UB30 for MAC configuration not populated NOTE Contact ISEE sales for custom assembly boards The Ethernetinterface supports the following features Fully compliant with IEEEE 802 3 802 3u standards 10BASE T and 100BASE ...

Страница 50: ...of processor board The audio codec in the TPS65950 device includes five DACs and two ADCs to provide multiple voice channels and stereo downlink channels The audio output stages on the device include stereo headset amplifiers two integrated class D amplifiers providing stereo differential outputs pre drivers for line outputs and an earpiece amplifier The input audio stages include three differenti...

Страница 51: ... respectively with Part Number SWITCHCRAFT 35RASMT2BHNTR or any other compatible J601 J602 are linked to the expansion connector J1 Signal Name Pin Description HSOL J640 4 Differential single ended headset Left Output HSOR J640 1 Differential single ended headset Right Output GND J640 5 Ground AUXL J650 4 Left stereo audio input AUXR J650 1 Right stereo audio input GND J650 5 Ground Table 16 J1 li...

Страница 52: ... RCx 52 Stereo Audio Output Connector J640 A 3 5mm standard stereo output audio jack is provided to access the stereo output of the onboard audio CODEC The Audio CODEC is provided by the TPS65950 Figure 63 Stereo Output J640 connector location Stereo Audio In connector J650 A 3 5mm standard stereo audio input jack is provided to access the stereo input of the onboard audio CODEC Figure 64 Stereo I...

Страница 53: ...nnel or EDID Enhanced Display ID support over I2C is provided in order to allow the identification of the LCD monitor type and settings IGEP v2 BOARD does not support the full HDMI interface and is used to provide the DVI D interface portion only The user must use a HDMI to DVI D cable or adapter to connect to a LCD monitor A standard HDMI cable can be used when connecting to a monitor with and HD...

Страница 54: ...igh Capacity SD 2 0 is an extension of the SD standard which increases card s storage capacity up to 32GB SDHC cards shares the same physical and electrical form factor as older SD 1 x cards allowing SDHC devices to support both newer SDHC cards and older SD cards 5 23 LED INDICATORS D240 D440 There are two bicolor LED provided with IGEP v2 that can be controlled by the user In total are like 4 in...

Страница 55: ...7 LED signals 6 EXPANSION CONNECTOR J990 GPIO An optionfor a single 28 pin header is provided on board to allow connection of various expansion cards that could be developed by users or other sources Due to multiplexing different signals can be provided oneach pin providing more than 24 real signal accesses The J990 connector is a 28 pin 2x14 dual row 2 54mm Figure 68 J990 detail Pins 1 2 27 and 2...

Страница 56: ...s nReset and REGEN signals from OMAP Processor WARNING J990 interface is at 1 8V on all signals Only 1 8V CMOS levels are supported DO NOT expose the header to higher values J990 connector is BeagleBoard compatible expansion connector http beagleboard org exceptfor pins J990 4 J990 6 and J990 10 that aren t the same signals Note that only IGEP v2 NO WIFI board has all J990 available other IGEP v2 ...

Страница 57: ...s you need are all available depends on the multiplexed function on a per pin basis Only one signal per pin is available at once WARNING J990 signals go directly to OMAP processor Improper use of this connector could result on permanent damage to this processor J990 mates with SAMTEC HLE series for bottom entry connection Figure 71 J990 counterparts SAMTEC FTS Serie SAMTEC TSW Serie SAMTEC HLE Ser...

Страница 58: ...9 hsusb3_tll_nxt mm3_rxdm safe_mode J990 4 OMAP mcbsp3_dx TPS65950 uart2_cts gpio_140 hsusb3_tll_d4 safe_mode J990 5 OMAP mmc2_dat6 P_Dn WiFi mmc2_dir_cmd cam_shutter mmc3_dat2 gpio_138 hsusb3_tll_dir safe_mode J990 6 OMAP mcbsp3_clkx TPS65950 uart2_tx gpio_142 hsusb3_tll_d6 safe_mode J990 7 OMAP mmc2_dat5 Reset BT mmc2_ dir_d1 cam_global_rst mmc3_dat1 gpio_137 hsusb3_tll_stp mm3_rxdp safe_mode J9...

Страница 59: ...tionalities of your IGEP v2 This board has been designedfor simplicity andis the best way toexpand functionalities of your IGEP v2 by adding enhanced ports and additional hardware It can be pluggedeasily into your boardwithout having to engineer the components yourself It is the perfect complement to experience with many extra features made simple and quick Here some of the capabilities you can ad...

Страница 60: ...EP RADAR LAMBDA This is an example of what can be developed with your IGEP v2 Complex data processing needed on radars can be done in quasi real time thanks to the OMAP processor capabilities The only interface between sensor and processor boards is EXPANSION CONNECTOR J990 We invite you to take a look to this product on our website http www igep es Figure 72 IGEP v2 EXPANSION BOARD GENERAL VIEW F...

Страница 61: ...UMENT FROM ISEE 2007 S L Ref MAN PR IGEP0020 RCx 61 8 MECHANICAL SPECIFICATIONS Figure 74 IGEP v2 RC Top view mechanical specification Get Mechanical drawings on http www igep es User Menu Download 01 Products IGEPv2 HW_Mechanical 1 All dimensions are in millimeters 2 Board size is 93 x 64 mm 3 3 mounting holes on the corners 3 6mm diameter 4 1 6mm pcb width 5 FR4 substrate 8 layers ...

Страница 62: ...V Output Voltage supplyon USB Host pins 4 7 5 5 2 V Output Current supply on USB Host pins 500 mA RS485 Driver Input High Voltage 2 V Input Low Voltage 0 8 V Maximum Data Rate 250 Kbps Receiver Output Voltage High 2 8 V Output Voltage Low 0 4 V Input Resistance 12 15 KOhms JTAG RealviewICE Tool 30 MHz XDS560 30 MHz XDS510 30 MHz Lauterbach tm 30 MHz microSD Voltage Mode 1 8V 1 71 1 8 1 89 Voltage ...

Страница 63: ... Bluetooth 2 0 Bluetoothspecification 2 0 Channel spacing 1 MHz Output Power 4 0 4 dBm Frequency range Rx Tx 2400 2483 5 MHz Sensitivity BER 0 1 1 2402MHz 81 73 dBm 81 73 dBm 2 2441MHz 81 73 dBm 3 2480MHz 79 5 73 dBm C I Performance BER 0 1 1 co channel ratio 60dBm input 7 6 11 dBm 2 1MHz ratio 60dBm input 2 5 0 dBm 3 2MHz ratio 60dBm input 42 6 30 dBm 1 Current Consumption with standard software ...

Страница 64: ...e 16 J1 links to J640 J650 audio interface connectors 51 Table 17 LED signals 55 Table 18 Expansion Connector signals 58 Table 19 Electrical Characteristics 63 11 LIST OF FIGURES Figure 1 IGEP v2 View 7 Figure 2 IGEP v2 GENERAL VIEW 8 Figure 3 IGEP v2 revision C Block Diagram 11 Figure 4 IGEP v2 revision C board top side components 12 Figure 5 IGEP v2 revision C board bottom side components 13 Fig...

Страница 65: ...v2 revision B and C Schematic JA42 38 Figure 40 IGEP v2 revision C JA41 JA42 counterparts 38 Figure 41 IGEP v2 revision C JC20 location 39 Figure 42 IGEP v2 revision C JC20 detail 39 Figure 43 IGEP v2 revision C schematic A D 40 Figure 44 IGEP v2 revision C schematic A D SPI interface 40 Figure 45 IGEP v2 revision C JC30 location 41 Figure 46 IGEP v2 revision C JC30 detail 41 Figure 47 IGEP v2 rev...

Страница 66: ...5 Figure 70 J990 Schematic 56 Figure 71 J990 counterparts 57 Figure 72 IGEP v2 EXPANSION BOARD GENERAL VIEW 60 Figure 73 IGEP v2 RADAR LAMBDA GENERAL VIEW 60 Figure 74 IGEP v2 RC Top view mechanical specification 61 12 KNOWN ISSUES 13 TROUBLESHOOTING 14 CHANGE HISTORY Revision Date Description 1 0 2012 02 15 Initial version 2 0 2013 02 06 http bug isee biz roadmap_page php version_id 26 0000084 bu...

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