Intersil HIP4086, Руководство пользователя

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Application Note 1829
5
AN1829.0
March 14, 2013
Theory of Operation
The HIP4086DEMO1Z demonstration board is a general purpose
3-phase BLDC motor controller. Three half bridge power circuits
drive the motor as shown in Figure 4.
Three 6 step bridge state logic diagrams, illustrated in Figure 5,
are used to drive the motor. The bridge state logic diagrams
represents the logic status of the each half bridge but the actual
voltage applied to the motor appears much differently. Figure 6
illustrates the bridge status logic vs the actual voltage waveforms
applied to each motor lead.
The HIP4086 has 6 driver outputs, AHO, ALO, BHO, BLO, CHO,
and CLO, to control the six bridge FETs individually. If the gate
drives for both FETs of one half bridge are low, current will not
flow in the corresponding motor lead (high impedance or Hi-
Z ). If
the gate drive for the low FET is high and the gate drive for the
high FET is low, then the phase node of that half bridge, and the
corresponding motor lead, is connected to ground (
L ow). If the
low and high gate drives are complementary driven, the phase
node can be pulse width modulated (
P WM) to control the
average voltage on that motor lead.
The motor rotation period and the amplitude of the bridge
voltage waveforms are modified by the microcontroller to control
the speed of the motor. Pulse width modulation is used to modify
the amplitude of the voltage waveforms and the motor rotation
period is established by the shaft position hall sensors that signal
the controller to change the switching sequence. Typical hall
sensor logic is illustrated in Figure 5. Each hall logic diagram, HA,
HB, and HC, correspond respectively to the bridge state logic
diagrams, MA, MB, and MC. For example, the transition of the
hall sensor logic, from step 1 to 2, results with the drive
waveform transition of
ZLP to PLZ where P , L , and Z define the
state of each half bridge.
FIGURE 4. BASIC BLDC MOTOR POWER TOPOLOGY
BLDC
MOTOR
AHO
ALO BHO
BLO
CHO
CLO
FIGURE 5. HALL SENSOR LOGIC vs BRIDGE STATE LOGIC
FIGURE 6. BRIDGE STATE LOGIC vs MOTOR VOLTAGE
000 100 110 111 011 000 100 110 111 011 001 001
HALL SENSOR LOGIC
HC
HB
HA
ZLP PLZ PZL ZPL LPZ LZP ZLP PLZ PZL ZPL LPZ LZP
MB
MA
MC
1 2 3 4 5 6 1 2 3 4 5 6
0° 60° 120° 180° 240°
Bridge State Logic: P = PWM, L = Low, Z = off
0° 60° 120° 180° 240° 0°
SEQUENCE STEP NUMBERS
Z
L
P
ZLP PLZ PZL ZPL LPZ LZP ZLP PLZ PZL ZPL LPZ LZP
MB
MA
MC
Bridge State Logic: P = PWM, L = Low, Z = off
IDEALIZED MOTOR VOLTAGE WAVEFORMS
MC
MB
MA
+Vbat
-Vbat
~ ½ Vbat
20kHz PWM freq.
Motor rotation period
per pole