13
H a l f S t e p M o d e
In half step mode the phasing alternates from one phase energized to two
phases energized. Half step mode is selected by a logic LOW on the Half/
Full step input.
T i m i n g
Figure 1.2.5: Timing
Figure 1.2.3: Wave Mode Phase Sequence
1
3
5
7
2
4
6
8
2
4
6
8
2
4
6
8
2
STEP CLOCK
PHASE A
PHASE B
PHASE A
PHASE B
Figure 1.2.4: Half Step Mode
1
3
5
7
2
4
6
8
1
2
3
4
5
6
7
8
1
STEP CLOCK
PHASE A
PHASE B
PHASE A
PHASE B
t
CLK
t
S
t
H
STEP CLOCK
CW/CCW
HALF/FULL STEP
Parameter Minimum
t
- Clock Time.......................3µs
t - Set up time...........................2µs
t - Hold Time..............................5.5µs
CLCK
S
H
Содержание IB S Series
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