29
Figure 1.5.3: TTL Interface
O p e n C o l l e c t o r I n t e r f a c e
Figure 1.5.4: Open Collector Interface
ENABLE
H
CW
LOGIC
GROUND
/F
STEP
CLOCK
/CCW
CURRENT
ADJUST
PHASE A
PHASE
PHASE B
PHASE
V+
GROUND
A
B
PIN 1
D
R
A
WN
B
Y
J
A
+5VDC
CONTROLLER
OUTPUT
430
Ω
1N916
OR EQUIV
.
TTL INTERFACE
INTERFACE SHOWN CONNECTED TO
THE ENABLE INPUT, MAY BE USED FOR
THE OTHER LOGIC INPUTS
T T L I n t e r f a c e
ENABLE
H
CW
LOGIC
GROUND
/F
STEP
CLOCK
/CCW
CURRENT
ADJUST
PHASE A
PHASE
PHASE B
PHASE
V+
GROUND
A
B
PIN 1
D
R
A
WN
B
Y
J
A
+VDC
CONTROLLER
OUTPUT
R
¼ W
OPEN COLLECTOR
INTERFACE
INTERFACE SHOWN CONNECTED TO
THE ENABLE INPUT, MAY BE USED FOR
THE OTHER LOGIC INPUTS
+VDC
5
10
12
15
24
430
1200
1500
2000
3000
R
Содержание IB S Series
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