Intel Xeon L3360, Техническое описание

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Land Listing and Signal Descriptions
70 Datasheet
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies
are stable and within their specifications. ‘Clean’ implies that the
signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until
they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at
any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should
be driven high throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#.
RESET# Input
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at least
one millisecond after V
CC
and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These configuration
options are described in the
Section 6.1 .
This signal does not have on-die termination and must be terminated
on the system board.
RESERVED
All RESERVED lands must remain unconnected. Connection of these
lands to V
CC
, V
SS
, V
TT
, or to any other signal (including each other)
can result in component malfunction or incompatibility with future
processors.
RS[2:0]# Input
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB agents.
SKTOCC# Output
SKTOCC# (Socket Occupied) will be pulled to ground by the
processor. System board designers may use this signal to determine
if the processor is present.
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor
will tri-state its outputs.
Table 4-3. Signal Description (Sheet 7 of 10)
Name Type Description