Intel Xeon L3360, Техническое описание

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Datasheet
69
Land Listing and Signal Descriptions
INIT# Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on Reset
vector configured during power-on configuration. The processor
continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal and must connect the appropriate pins/lands
of all processor FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
ITP_CLK[1:0] Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
LINT[1:0] Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/
lands of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor.
Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of all
processor FSB agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction to the end of
the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity of
lock.
MSID[1:0] Output
On a Yorkfield processor these signals are not connected on the
package (they are floating). As an alternative to MSID, Intel has
implemented the Power Segment Identifier (PSID) to report the
maximum Thermal Design Power of the processor. Refer to the
Platform Design Guide for additional information regarding PSID.
PECI
Input/
Output
PECI is a proprietary one-wire bus interface. See Chapter 5.3 for
details.
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This indicates
that the processor Thermal Control Circuit (TCC) has been activated,
if enabled. As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled. The TCC will remain active until the
system de-asserts PROCHOT#. See
Section 5.2.4 for more details.
Table 4-3. Signal Description (Sheet 6 of 10)
Name Type Description