Intel Xeon L3360, Техническое описание

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Electrical Specifications
28 Datasheet
2.9 Clock Specifications
2.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to Table 2-14 for the processor supported ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
NOTES:
1.
Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
2.9.2 FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-15 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
Table 2-14. Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core
Frequency to FSB
Frequency
Core Frequency
(333 MHz BCLK/1333
MHz FSB)
Notes
1, 2
1/6
2 GHz
-
1/7
2.33 GHz
-
1/7.5
2.50 GHz
-
1/8
2.66 GHz
-
1/8.5
2.83 GHz
-
1/9
3 GHz
-
1/9.5
3.16 GHz
-
1/10
3.33 GHz
-
1/10.5
3.50 GHz
-
1/11
3.66 GHz
-
1/11.5
3.83 GHz
-
1/12
4 GHz
-
1/12.5
4.16 GHz
-
1/13
4.33 GHz
-
1/13.5
4.50 GHz
-
1/14
4.66 GHz
-
1/15
5 GHz
-