Intel® Xeon® Processor 5600 Series
28
Specification Update, March 2010
Workaround:
As long as machine check exceptions are enabled, the machine check exception
handler can log the TLB error prior to core C6 entry. This will ensure the error is logged
before it is cleared.
Status:
For the steppings affected, see the
BD36.
Changing the Memory Type for an In-Use Page Translation May Lead
to Memory-Ordering Violations
Problem:
Under complex micro-architectural conditions, if software changes the memory type for
data being actively used and shared by multiple threads without the use of semaphores
or barriers, software may see load operations execute out of order.
Implication:
Memory ordering may be violated. Intel has not observed this erratum with any
commercially available software.
Workaround:
Software should ensure pages are not being actively used before requesting their
memory type be changed.
Status:
For the steppings affected, see the
BD37.
A String Instruction that Re-maps a Page May Encounter an
Unexpected Page Fault
An unexpected page fault (#PF) may occur for a page under the following conditions:
• The paging structures initially specify a valid translation for the page.
• Software modifies the paging structures so that there is no valid translation for the
page (for example, by clearing to 0 the present bit in one of the paging-structure
entries used to translate the page).
• An iteration of a string instruction modifies the paging structures so that the
translation is again a valid translation for the page (e.g., by setting to 1 the bit that
was cleared earlier).
• A later iteration of the same string instruction loads from a linear address on the
page.
Problem:
Software did not invalidate TLB entries for the page between the first modification of
the paging structures and the string instruction. In this case, the load in the later
iteration may cause a page fault that indicates that there is no translation for the page
(for example, with bit 0 clear in the page-fault error code, indicating that the fault was
caused by a not-present page).
Implication:
Software may see an unexpected page fault that indicates that there is no translation
for the page. Intel has not observed this erratum with any commercially available
software or system.
Workaround:
Software should not update the paging structures with a string instruction that
accesses pages mapped the modified paging structures.
Status:
For the steppings affected, see the
BD38.
Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode
Interrupt is Received while All Cores in C6
Problem:
If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is
pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will
