Intel® Xeon® Processor 5600 Series
34
Specification Update, March 2010
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
Problem:
This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPT-
induced VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag
values that the EFLAGS register would have held had the instruction completed without
fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if
its delivery causes a nested fault.
Implication:
None identified. Although the EFLAGS value saved by an affected event (a page fault or
an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not
identified software that is affected by this erratum. This erratum will have no further
effects once the original instruction is restarted because the instruction will produce the
same results as if it had initially completed without fault or VM exit.
Workaround:
If the handler of the affected events inspects the arithmetic portion of the saved
EFLAGS value, then system software should perform a synchronized paging structure
modification and TLB invalidation.
Status:
For the steppings affected, see the
BD57.
System May Hang if
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL Commands
Are Not Issued in Increasing Populated DDR3 Rank Order
Problem:
ZQCL commands are used during initialization to calibrate DDR3 termination. A ZQCL
command can be issued by writing 1 to the
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL (Device 4,5,6, Function 0,
Offset 15, bit[15]) field and it targets the DDR3 rank specified in the RANK field
(bits[7:5]) of the same register. If the ZQCL commands are not issued in increasing
populated rank order then ZQ calibration may not complete, causing the system to
hang.
Implication:
Due to this erratum the system may hang if writes to the
MC_CHANNEL_{0,1,2}_MC_DIMM_INIT_CMD.DO_ZQCL field are not in increasing
populated DDR3 rank order.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the
BD58.
Package C3/C6 Transitions When Memory 2x Refresh is Enabled May
Result in a System Hang
Problem:
If ASR_PRESENT (MC_CHANNEL_{0,1,2}_REFRESH_THROTTLE_SUP PORT CSR
function 0, offset 68H, bit [0], Auto Self Refresh Present) is clear which indicates that
high temperature operation is not supported on the DRAM, the memory controller will
not enter self-refresh if software has REF_2X_NOW (bit 4 of the MC_CLOSED_LOOP
CSR, function 3, offset 84H) set. This scenario may cause the system to hang during
C3/C6 entry.
Implication:
Failure to enter self-refresh can delay C3/C6 power state transitions to the point that a
system hang may result with CATERR being asserted. REF_2X_NOW is used to double
the refresh rate when the DRAM is operating in extended temperature range. The
