Intel® Xeon® Processor 5600 Series
35
Specification Update, March 2010
ASR_PRESENT was intended to allow low power self refresh with DRAM that does not
support automatic self refresh.
Workaround:
It is possible for Intel provided BIOS reference code to contain a workaround for this
erratum. Please refer to the latest version of the BIOS memory Reference Code and
release notes.
Status:
For the steppings affected, see the
BD59.
Back to Back Uncorrected Machine Check Errors May Overwrite
IA32_MC3_STATUS.MSCOD
Problem:
When back-to-back uncorrected machine check errors occur that would both be logged
in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16])
field may reflect the status of the most recent error and not the first error. The rest of
the IA32_MC3_STATUS MSR contains the information from the first error.
Implication:
Software should not rely on the value of IA32_MC3_STATUS.MSCOD if
IA32_MC3_STATUS.OVER (bit [62]) is set.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD60.
Corrected Errors With a Yellow Error Indication May be Overwritten by
Other Corrected Errors
Problem:
A corrected cache hierarchy data or tag error that is reported with
IA32_MCi_STATUS.MCACOD (bits [15:0]) with value of 000x_0001_xxxx_xx01 (where
x stands for zero or one) and a yellow threshold-based error status indication (bits
[54:53] equal to 10B) may be overwritten by a corrected error with a no tracking
indication (00B) or green indication (01B).
Implication:
Corrected errors with a yellow threshold-based error status indication may be
overwritten by a corrected error without a yellow indication.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD61.
Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
Problem:
The performance monitor events DCACHE_CACHE_LD (Event 40H) and
DCACHE_CACHE_ST (Event 41h) count cacheable loads and stores that hit the L1
cache. Due to this erratum, in addition to counting the completed loads and stores, the
counter will incorrectly count speculative loads and stores that were aborted prior to
completion.
Implication:
The performance monitor events DCACHE_CACHE_LD and DCACHE_CACHE_ST may
reflect a count higher than the actual number of events.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD62.
Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
Problem:
The performance monitor event INSTR_RETIRED (Event C0H) should count the number
of instructions retired, and MEM_INST_ RETIRED (Event 0BH) should count the number
