Intel® Xeon® Processor 5600 Series
37
Specification Update, March 2010
BD66.
Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than
Expected
Problem:
x87 instructions that trigger #MF normally service interrupts before the #MF. Due to
this erratum, if an instruction that triggers #MF is executed while Enhanced Intel
SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or
Thermal Monitor events occur, the pending #MF may be signaled before pending
interrupts are serviced.
Implication:
Software may be observed #MF being-signaled before pending interrupts are serviced.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD67.
VM Exits Due to “NMI-Window Exiting” May Be Delayed by One
Instruction
Problem:
If VM entry is executed with the “NMI-window exiting” VM-execution control set to 1, a
VM exit with exit reason “NMI window” should occur before execution of any instruction
if there is no virtual-NMI blocking, no blocking of events by MOV SS, and not blocking
of events by STR. If VM entry is made with no virtual-NMI blocking but with blocking of
events by either MOV SS or STI, such a VM exit should occur after execution of one
instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed
by one additional instruction.
Implication:
VMM software using “NMI-window exiting” for NMI virutalization should generally be
unaffected, as the erratum causes at most a one-instruction delay in the injection of a
virtual NMI, which is virtually asynchronous. The erratum may affect VMMs relying on
deterministic delivery of the affected VM exits.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD68.
Multiple Performance Monitor Interrupts are Possible on Overflow of
IA32_FIXED_CTR2
Problem:
When multiple performance counters are set to generate interrupts on an overflow and
more than one counter overflows at the same time, only one interrupt should be
generated. However, if one of the counters set to generate an interrupt on overflow is
the IA32_FIXED_CTR2 (MSR 30BH) counter, multiple interrupts may be generated
when the IA32_FIXED_CTR2 overflows at the same time as any of the other
performance counters.
Implication:
Multiple counter overflow interrupts may be unexpectedly generated.
Workaround:
None identified.
Status:
For the steppings affected, see the
BD69.
C-State Autodemotion May be too Aggressive Under Certain
Configurations and Workloads
Problem:
The C-state autodemotion feature allows the processor to make intelligent power and
performance tradeoffs regarding the OS-requested C-state. Under certain operating
system and workload specific conditions, the C-state auto-demotion feature may be
