Intel UPI- 41A, Руководство пользователя

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UPI-41A/41AH/42/42AH USER’S MANUAL
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Figure 2-17. Interface to 8080 System Bus
Table 2-4. Data Transfer Controls
CS RD WR A
0
0 0 1 0 Read DBBOUT register
0 0 1 1 Read STATUS register
0 1 0 0 Write DBBIN data register
0 1 0 1 Write DBBIN command register
1 x x x Disable DBB
Status Read
Table 2-4 shows the logic sequence required for a
STATUS register read. When CS and RD are low with
A
0
high, the contents of the 8-bit status register appears
on Data lines D
0
– D
7
.
Data Write
Table 2-4 shows the sequence for writing information
to the DBBIN register. When CS and WR are low, the
contents of the system data bus is latched into DBBIN.
Also, the IBF flag is set and an interrupt is generated, if
enabled.
Command Write
During any write (Table 2-4), the state of the A
0
input
is latched into the status register in the F
1
(command/
data) flag location. This additional bit is used to signal
whether DBBIN contents are command (A
0
e
1) or
data (A
0
e
0) information.
INPUT/OUTPUT INTERFACE
The UPI-41A/41AH/42/42AH has 16 lines for input
and output functions. These I/O lines are grouped as
two 8-bit TTL compatible ports: PORTS 1 and 2. The
port lines can individually function as either inputs or
outputs under software control. In addition, the lower 4
lines of PORT 2 can be used to interface to an 8243 I/O
expander device to increase I/O capacity to 28 or more
lines. The additional lines are grouped as 4-bit ports:
PORTS 4, 5, 6, and 7.
PORTS 1 and 2
PORTS 1 and 2 are each 8 bits wide and have the same
I/O characteristics. Data written to these ports by an
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