Intel® Server Board S2600WF Product Family Technical Product Specification
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5.
PCIe* Support
The PCI Express* (PCIe*) interface of the Intel® Server Board S2600WF product family is fully compliant with
the PCIe Base Specification, Revision 3.0 supporting the following PCIe bit rates: Gen 3.0 (8.0 GT/s), Gen 2.0
(5.0 GT/s), and Gen 1.0 (2.5 GT/s).
For specific board features and functions supported by the PCIe sub-system, see Chapter 6. Table 12
provides the PCIe port routing information from each processor:
Table 12. CPU - PCIe* port routing
CPU 1
CPU 2
PCI Ports
Onboard Device
PCI Ports
Onboard Device
Port DMI 3 - x4
Chipset
Port DMI 3 - x4
Riser Slot #3
Port 1A - x4
Riser Slot #1
Port 1A - x4
Riser Slot #2
Port 1B - x4
Riser Slot #1
Port 1B - x4
Riser Slot #2
Port 1C – x4
Riser Slot #1
Port 1C – x4
Riser Slot #1
Port 1D – x4
Riser Slot #1
Port 1D – x4
Riser Slot #1
Port 2A - x4
Chipset (PCH) - uplink
Port 2A - x4
Riser Slot #2
Port 2B - x4
Chipset (PCH) - uplink
Port 2B - x4
Riser Slot #2
Port 2C - x4
Chipset (PCH) - uplink
Port 2C - x4
Riser Slot #2
Port 2D - x4
Chipset (PCH) - uplink
Port 2D - x4
Riser Slot #2
Port 3A - x4
SAS Module
Port 3A - x4
OCuLink PCIe_SSD2
Port 3B - x4
SAS Module
Port 3B - x4
OCulink PCIe_SSD3
Port 3C - x4
OCuLink PCIe_SSD0
Port 3C - x4
Riser Slot #3
Port 3D -x4
OCuLInk PCIe_SSD1
Port 3D -x4
Riser Slot #3
5.1.1
PCIe* Enumeration and Allocation
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local Bus
Specification, Revision 3.0. The bus number is incremented when the BIOS encounters a PCI-PCI bridge
device.
Scanning continues on the secondary side of the bridge until all subordinate buses are assigned numbers.
PCI bus number assignments may vary from boot to boot with varying presence of PCI devices with PCI-PCI
bridges.
If a bridge device with a single bus behind it is inserted into a PCI bus, all subsequent PCI bus numbers below
the current bus are increased by one. The bus assignments occur once, early in the BIOS boot process, and
never change during the pre-boot phase.
The BIOS resource manager assigns the PIC-mode interrupt for the devices that are accessed by the legacy
code. The BIOS ensures that the PCI BAR registers and the command registers for all devices are correctly set
up to match the behavior of the legacy BIOS after booting to a legacy OS. Legacy code cannot make any
assumption about the scan order of devices or the order in which resources are allocated to them. The BIOS
automatically assigns IRQs to devices in the system for legacy compatibility. A method is not provided to
manually configure the IRQs for devices.
5.1.2
Non-Transparent Bridge
The PCIe Non-Transparent Bridge (NTB) acts as a gateway that enables high performance, low latency
communication between two PCIe Hierarchies, such as a local and remote system. The NTB allows a local
