Intel® Server Board S2600WF Product Family Technical Product Specification
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4.4
Memory RAS Features
Supported memory RAS features are dependent on the level of processor installed. Each processor level
within the Intel Xeon processor Scalable family has support for either standard or advanced memory RAS
features as defined in Table 11.
Table 11. Memory RAS features
RAS Feature
Description
Standard Advanced
Device Data Correction
x8 Single Device Data Correction (SDDC) via static virtual lockstep
(Applicable to x8 DRAM DIMMs)
√
√
Adaptive Data Correction (SR) (Applicable to x4 DRAM DIMMs)
√
√
x8 Single Device Data Corr 1 bit (SDDC+1) (Applicable to x8
DRAM DIMMs)
√
SDDDC + 1, and ADDDC (MR) + 1 (Applicable to x4 DRAM DIMMs)
√
DDR4 Command/Address
Parity Check and Retry
DDR4 Command/Address Parity Check and Retry:
Is a DDR4 technology based CMD/ADDR parity check and retry with
following attributes:
•
CMD/ADDR Parity error “address“ logging
•
CMD/ADDR Retry
√
√
DDR4 Write Data CRC
Protection
DDR4 Write Data CRC Protection detects DDR4 data bus faults during
write operation.
√
√
Memory Demand and Patrol
Scrubbing
Demand scrubbing is the ability to write corrected data back to the
memory once a correctable error is detected on a read transaction.
Patrol scrubbing proactively searches the system memory, repairing
correctable errors. Prevents accumulation of singlebit errors.
√
√
Memory Mirroring
Full Memory Mirroring: An intra IMC method of keeping a duplicate
(secondary or mirrored) copy of the contents of memory as a redundant
backup for use if the primary memory fails. The mirrored copy of the
memory is stored in memory of the same processor socket's IMC.
Dynamic (without reboot) failover to the mirrored DIMMs is transparent
to the OS and applications.
√
√
Address Range/Partial Memory Mirroring: Provides further intra socket
granularity to mirroring of memory by allowing the firmware or OS to
determine a range of memory addresses to be mirrored, leaving the rest
of the memory in the socket in non-mirror mode.
√
Sparing
•
Rank Level Memory Sparing
•
Multi-rank Level Memory
Sparing
Dynamic fail-over of failing Ranks to spare Ranks behind the same
memory controller DDR ranks.
√
√
With Multi Rank up to two ranks out of a maximum of eight ranks can be
assigned as spare ranks.
√
√
iMC’s Corrupt Data
Containment
Corrupt Data Containment is a process of signaling error along with the
detected UC data. iMC's patrol scrubber and sparing engine have the
ability to poison the UC data.
√
√
Failed DIMM Isolation
Ability to identify a specific failing DIMM thereby enabling the user to
replace only the failed DIMM(s). In case of uncorrected error and
lockstep mode, only DIMM-pair level isolation granularity is supported.
√
√
Memory Disable and Map Out
for FRB
Allows memory initialization and booting to OS even when memory
fault occurs.
√
√
Post Package Repair
Starting with DDR4 technology there is an additional capability
available known as PPR (Post Package Repair). PPR offers additional
spare capacity within the DDR4 DRAM that can be used to replace faulty
cell areas detected during system boot time.
√
√
Note: RAS features may not be supported on all SKUs of a processor type.
