Intel® Server Board S2600WF Product Family Technical Product Specification
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12.2.3
System Initialization
During system initialization, both the BIOS and the BMC initialize the items described in the following
sections.
12.2.3.1
Processor Tcontrol Setting
Processors used with this chipset implement a feature called Tcontrol, which provides a processor-specific
value that can be used to adjust the fan-control behavior to achieve optimum cooling and acoustics. The
BMC reads these from the CPU through PECI Proxy mechanism provided by Intel® ME. The BMC uses these
values as part of the fan-speed-control algorithm.
12.2.3.2
Fault Resilient Booting (FRB)
Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that allow a
multiprocessor system to boot even if the bootstrap processor (BSP) fails. Only FRB-2 is supported using
watchdog timer commands.
FRB-2 refers to the FRB algorithm that detects system failures during POST. The BIOS uses the BMC
watchdog timer to back up its operation during POST. The BIOS configures the watchdog timer to indicate
that the BIOS is using the timer for the FRB2 phase of the boot operation.
After the BIOS has identified and saved the BSP information, it sets the FRB-2 timer use bit and loads the
watchdog timer with the new timeout interval.
If the watchdog timer expires while the watchdog use bit is set to FRB-2, the BMC (if so configured) logs a
watchdog expiration event showing the FRB-2 timeout in the event data bytes. The BMC then hard resets the
system, assuming the BIOS-selected reset as the watchdog timeout action.
The BIOS is responsible for disabling the FRB-2 timeout before initiating the option ROM scan and before
displaying a request for a boot password. If the processor fails and causes an FRB-2 timeout, the BMC resets
the system.
The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired FRB-2 timer, the
BIOS enters the failure in the system event log (SEL). In the OEM bytes entry in the SEL, the last POST code
generated during the previous boot attempt is written. FRB-2 failure is not reflected in the processor status
sensor value.
The FRB-2 failure does not affect the front panel LEDs.
12.2.3.3
Post Code Display
The BMC, upon receiving standby power, initializes internal hardware to monitor port 80h (POST code)
writes. Data written to port 80h is output to the system POST LEDs. The BMC deactivates POST LEDs after
POST completes. Refer to Appendix B for a complete list of supported POST code diagnostic LEDs.
12.2.4
Watchdog Timer
The BMC implements a fully IPMI 2.0 compatible watchdog timer. For details, see the
Intelligent Platform
Management Interface Specification Second Generation v2.0
. The NMI/diagnostic interrupt for an IPMI 2.0
watchdog timer is associated with an NMI. A watchdog pre-timeout SMI or equivalent signal assertion is not
supported.
12.2.5
System Event Log (SEL)
The BMC implements the system event log as specified in the
Intelligent Platform Management Interface
Specification v2.0
. The SEL is accessible regardless of the system power state through the BMC's in-band and
out-of-band interfaces.
The BMC allocates 95,231 bytes (approx. 93 KB) of non-volatile storage space to store system events. The
SEL timestamps may not be in order. Up to 3,639 SEL records can be stored at a time. Because the SEL is
