Development Kit User’s Guide
October 2008
Order Number: 320067-002US
23
System Overview—Intel
®
EP80579 Integrated Processor with Intel
®
QuickAssist Technology
3.3
Platform Reset
Figure 6
depicts the reset logic for the Intel
®
EP80579 Development Board.
Figure 6.
Reset Diagram
E
P
80
579
WD
T_
N
PW
RB
TN_
N
RS
M
R
S
T
_
N
SY
S_
REST
_
N
PCI
R
ST
_
N
PL
T
R
ST
_
N
PW
RO
K
VR
M
P
W
R
G
D
PW
RG
D
R
S
T
IN
_
N
R
T
EST
_
N
PW
R
O
N_
BTN
FP_
P
W
R
O
N
#
RT
CRST
#
RT
C
R
ESE
T_
BT
N
FP
_R
ESE
T#
RS
M
R
S
T
_
N
Fr
om
s
u
pe
r I
O
CPU
_
V
RD_
PW
R_
GD
S
YS_
PW
R_
O
K
FW
H
LA
I
SIO
LP
C
P8
0
PC
I-
E x
4
c
o
n
n
PCI
-E x
8
c
o
n
n
SY
S_
PW
R_
O
K
GB
E
_
A
U
X
_
P
W
R_
GOOD
G
B
E
_
PM
E
_
W
AKE
G
B
E
_
aux
_p
w
r_
g
o
o
d
Wa
ke si
gn
al
TP
M
VR
M
re
a
d
y
f
o
r
C
P
U
0.
9-
1
.20
V
CK4
1
0
V
c
csu
s25
2.
5V
V
c
cp
sus
3
.3
v
V
c
csu
s1
1
.2
v
2.
5
V
f
o
r
G
B
E
V
R
M
re
a
d
y
fo
r
CO
R
E
1
.2
V
SIL
V
E
R
BO
X
_
PW
RO
K
G
B
E Po
we
r g
o
o
d
2m
s
De
la
y
100
m
s
De
la
y
DDR2
1
.8
V
PM
E
_
N
PC
I-
E s
w
it
c
h
D
DR_
PW
R
O
K
VSB
Y3
_
3
D_
R
E
SE
T
_
L
Te
s
t p
o
in
t
EN
PW
R
G
D
PWR
GD
EN
PW
R G
D
0
ohm
em
pt
y
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