Intel
®
EP80579 Integrated Processor with Intel
®
QuickAssist Technology—System Overview
Development Kit User’s Guide
October 2008
22
Order Number: 320067-002US
3.2
Platform Clocking
The Intel
®
EP80579 Development Board uses one CK-410 clock synthesizer to generate
the host differential pair clocks and the 100 MHz differential clock to the DB800. The
DB800 then generates the 100 MHz differential pair clock for PCI Express devices.
Figure 5
shows the board clocking configuration.
Figure 5.
Clock Block Diagram
ITP
Po
rt
8
0
SI
O
IT
P_BC
LK
100M
H
z
_C
OR
E_D
if
f
F
W
H
_33M
H
Z
_C
LK
FW
H
POR
T
80_33M
H
Z
_C
LK
IC
H
_33M
H
Z
_C
LK
SI
O
_33M
H
Z
_C
LK
LPC
_14M
H
Z
_C
LK
LPC
_14M
H
Z
_C
LK
ICH_
U
S
B
_
4
8
M
H
Z
_
CL
K
32.786 kHz
D
D
R
_
C
M
D
C
L
K
[0
..
3
]
ICH_SUS
CLK
PC
I Exp
re
s
s
M
id
bus
EX
P_
SLOT
2_100
M
H
Z
_
C
L
K
EXP_T
EST
_100
M
H
Z
_
C
L
K
G
b
E
PH
Y
125M
H
Z
_
C
L
K
SAT
A_100M
H
Z
_D
if
f
Me
m
o
ry
1
4
.3 1
8
M
H
z
S
M
A
D
B
800
TP
M
T
P
M
_33M
H
Z
_C
L
K
EX
P_
SLOT
1_100
M
H
Z
_
C
L
K
PC
I Exp
ress
Sl
o
t
E
1
/ T1
I
/O
L
E
B Co
nn
e
c
to
rs
33 M
H
z
33M
H
Z
PC
I-
E_100M
H
Z
_D
if
f
C
K
-410
8.
19
2 M
H
z
25M
H
Z
_C
LK
EXP
_
B
F
1_10
0M
H
Z
_C
LK
EXP
_
B
F
2_10
0M
H
Z
_C
LK
EXP
_
B
F
3_10
0M
H
Z
_C
LK
EXP
_
B
F
4_10
0M
H
Z
_C
LK
EXP
_
B
F
5_10
0M
H
Z
_C
LK
PC
Ie
5P S
w
it
ch
Sl
o
t 1
Sl
o
t 2
Sl
o
t 3
Sl
o
t 4
Fa
nou
t
B
u
ffer
25
M
H
z
C
rystal
Os
c
On
Mezzanines
EP80579
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