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Power Management

38

Datasheet, Volume 1

4.3.2

Self Refresh

The Uncore Power Manager (PCU) may request the memory controller to place the
DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put
the channel in self refresh if software remaps memory to use a subset of all channels.
Also processor channels can enter self refresh autonomously without PCU instruction
when the package is in a package C0 state.

4.3.2.1

Self Refresh Entry

Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter
always clears with any access to the memory controller and remains clear as long as
the memory controller is not drained. As soon as the memory controller is drained, the
counter starts counting, and when it reaches the idle-count, the memory controller will
place the DRAMs in self refresh state.

Power may be removed from the memory controller core at this point, but the V

CCD

supply (1.5 V) to the DDR I/O must be maintained.

4.3.2.2

Self Refresh Exit

Self refresh exit can be either a message from an external unit (PCU in most cases, but
also possibly from any message-channel master) or as reaction for an incoming
transaction.

The proper actions on self refresh exit are:

• CK is enabled, and four CK cycles driven
• When proper skew between Address/Command and CK are established, assert CKE
• Issue NOPs for tXSRD cycles
• Issue ZQCL to each rank
• The global scheduler will be enabled to issue commands

4.3.2.3

DLL and PLL Shutdown

Self refresh, according to configuration, may be a trigger for master DLL shut-down
and PLL shut-down. The master DLL shut-down is issued by the memory controller
after the DRAMs have entered self refresh.

The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a
signal from PLL indicating that the memory controller can start working again.

4.3.3

DRAM I/O Power Management

Unused signals are tristated to save power. This includes all signals associated with an
unused memory channel.

The I/O buffer for an unused signal should be tristated (output driver disabled), the
input receiver (differential sense-amp) should be disabled. The input path must be
gated to prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).

4.4

DMI2 / PCI Express* Power Management

Active State Power Management (ASPM) support using the L1 state.

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Содержание BX80619I73960X

Страница 1: ...LGA 2011 Socket Datasheet Volume 1 Supporting Desktop Intel Core i7 3960X and i7 3970X Extreme Edition Processor for the LGA 2011 Socket Supporting Desktop Intel Core i7 39xxK and i7 38xx Processor S...

Страница 2: ...pec Finder or contact your Intel representative for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting oper...

Страница 3: ...2 3 1 DMI2 Error Flow 19 2 3 2 DMI2 Link Down 20 2 4 Platform Environment Control Interface PECI 20 3 Technologies 21 3 1 Intel Virtualization Technology Intel VT 21 3 1 1 Intel Virtualization Technol...

Страница 4: ...wn 37 4 3 2 Self Refresh 38 4 3 2 1 Self Refresh Entry 38 4 3 2 2 Self Refresh Exit 38 4 3 2 3 DLL and PLL Shutdown 38 4 3 3 DRAM I O Power Management 38 4 4 DMI2 PCI Express Power Management 38 5 The...

Страница 5: ...Lane Partitioning and Direct Media Interface Gen 2 DMI2 12 2 1 PCI Express Layering Diagram 18 2 2 Packet Flow through the Layers 18 4 1 Idle Power Management Breakdown of the Processor Cores 31 4 2 T...

Страница 6: ...als with On Die Termination 59 7 7 Power On Configuration Option Lands 59 7 8 Processor Absolute Minimum and Maximum Ratings 60 7 9 Voltage Specification 61 7 10 Current Icc_Max and Icc_TDC Specificat...

Страница 7: ...me 1 7 Revision History Revision Number Description Revision Date 001 Initial Release November 2011 002 Updated to clarify references to PCI Express Added Intel Core i7 3970X Processor Extreme Edition...

Страница 8: ...8 Datasheet Volume 1...

Страница 9: ...integrated memory controller IMC and integrated I O IIO such as PCI Express and DMI2 on a single silicon die This single die solution is known as a monolithic processor This document is Volume 1 of th...

Страница 10: ...VT Intel Virtualization Technology for Directed I O Intel VT d Intel Virtualization Technology Intel Core i7 processor family for the LGA 2011 socket Extensions Intel 64 Architecture Intel Streaming S...

Страница 11: ...lanes of PCI Express interconnect for general purpose PCI Express devices capable of up to 8 0 GT s speeds that are configurable for up to 10 independent ports Negotiating down to narrower widths is...

Страница 12: ...4 Port 1b Transaction Link Physical 0 3 X4 Port 1a Port 1 IOU2 PCIe X8 Port 1a 8 11 Transaction Link Physical 0 3 Port 2 IOU0 PCIe X4 Port 2b X4 Port 2a X8 Port 2a X4 Port 2d X4 Port 2c X8 Port 2c X16...

Страница 13: ...e see Section 1 7 Related Documents for additional details on PECI services available in the processor Supports operation at up to 2 Mbps data transfers Link layer improvements to support additional s...

Страница 14: ...s not needed Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non exec...

Страница 15: ...trol Unit PCIe PCI Express PECI Platform Environment Control Interface Processor The 64 bit single core or multi core component package Processor Core The term processor core refers to Si die itself w...

Страница 16: ...l Core i7 Processor Family for the LGA 2011 Socket Specification Update 326198 Desktop Intel Core i7 Processor Family for the LGA 2011 Socket Thermal Mechanical Specifications and Design Guide 326199...

Страница 17: ...lock and 2n indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration 2 2 PCI Express Interface This section describes...

Страница 18: ...y of Transaction Layer Packets TLPs TLPs are used to communicate transactions such as read and write as well as certain types of events The Transaction Layer also manages flow control of TLPs 2 2 1 2...

Страница 19: ...the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the Conventional PCI Specification PCI Express configuration space is divided into a PCI compatible regio...

Страница 20: ...begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1 PECI also includes variable...

Страница 21: ...to support and improve I O virtualization performance and robustness The Intel VT d specification and other Intel VT documents can be referenced at http www intel com technology virtualization index h...

Страница 22: ...ask segment selector A VMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software 3 1 3 Intel Virtualizatio...

Страница 23: ...3 1 3 2 Intel Virtualization Technology Intel VT for Directed I O Intel VT d Processor Feature Additions The following are new features supported in Intel VT d on the processor Improved invalidation a...

Страница 24: ...attacks that threaten table based software implementations of AES In addition these instructions make AES simple to implement with reduced code size This helps reducing the risk of inadvertent introd...

Страница 25: ...given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay with its TDP limit Note Intel Turbo Boost Technology is only active if th...

Страница 26: ...ware infrastructure across existing and new application domains 256 bit vector data sets can be processed up to twice the throughput of 128 bit data sets Application performance can scale up with numb...

Страница 27: ...scribed in this section 4 1 1 System States 4 1 2 Processor Package and Core States Table 4 2 lists the package C state support as the shallowest core C state that allows entry into the package C stat...

Страница 28: ...C Fully Flushed Notes1 PC0 Active CC0 N A No No 2 PC2 Snoopable Idle CC3 CC7 PCIe PCH and Remote Socket Snoops PCIe PCH and Remote Socket Accesses Interrupt response time requirement DMI Sidebands Con...

Страница 29: ...e takes 3 5 DCLK cycles until the first command is allowed and 16 cycles until first data is allowed Register CKE Power Down IBT ON mode Both CKE s are de asserted the Input Buffer Terminators IBTs ar...

Страница 30: ...is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signal...

Страница 31: ...t the thread and core level are shown in Figure 4 2 While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are aut...

Страница 32: ...are trapped and emulate MWAIT like functionality Any P_LVLx reads outside of this range do not cause an I O redirection to MWAIT Cx like request They fall through like a normal I O instruction Note W...

Страница 33: ...a P_LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts Dur...

Страница 34: ...is masked the processor attempts to re enter its previous package state If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a high...

Страница 35: ...he processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage Autonomous power reduction actions that are based on idle timers can trigger depe...

Страница 36: ...At least one core is in the C3 state The other cores are in a C3 or lower power state and the processor has been granted permission by the platform L3 shared cache retains context and becomes inaccess...

Страница 37: ...own mode The memory controller transitions the DRAM to power down by de asserting CKE and driving a NOP command The memory controller will tri state all DDR interface lands except CKE de asserted and...

Страница 38: ...so possibly from any message channel master or as reaction for an incoming transaction The proper actions on self refresh exit are CK is enabled and four CK cycles driven When proper skew between Addr...

Страница 39: ...ermal Management Specifications 5 Thermal Management Specifications For thermal specifications and design guidelines refer to the processor Thermal Mechanical Specification and Design Guide see Sectio...

Страница 40: ...Thermal Management Specifications 40 Datasheet Volume 1...

Страница 41: ...ch signal selects one rank as the target of the command and address DDR 0 1 2 3 _DQ 63 00 Data Bus DDR3 Data bits DDR 0 1 2 3 _DQS_DP 08 00 DDR 0 1 2 3 _DQS_DN 08 00 Data strobes Differential pair Dat...

Страница 42: ...ile DDR_SDA_C23 is used for memory channels 2 and 3 DDR_VREFDQRX_C01 DDR_VREFDQRX_C23 Voltage reference for system memory reads DDR_VREFDQRX_C01 is used for memory channels 0 and 1 while DDR_VREFDQRX_...

Страница 43: ...ut PE2C_TX_DN 11 8 PE2C_TX_DP 11 8 PCIe Transmit Data Output PE2D_TX_DN 15 12 PE2D_TX_DP 15 12 PCIe Transmit Data Output Table 6 5 PCI Express Port 3 Signals Signal Name Description PE3A_RX_DN 3 0 PE3...

Страница 44: ...to be connected as if the link is being used even when PCIe is not used PE_VREF_CAP PCI Express voltage reference used to measure the actual output voltage and comparing it to the assumed voltage A 0...

Страница 45: ...essor debug readiness PREQ_N Probe Mode Request is used by debug tools to request debug operation of the processor TCK TCK Test Clock provides the clock input for the processor Test Bus also known as...

Страница 46: ...level mode the output indicates that a particular branch of memory subsystem is hot MEM_HOT_C01_N is used for memory channels 0 1 while MEM_HOT_C23_N is used for memory channels 2 3 PMSYNC Power Mana...

Страница 47: ...P_N will again be asserted after RESET_N is de asserted This signal can also be asserted if the system memory interface has exceeded a critical temperature limit set by BIOS This signal is sampled aft...

Страница 48: ...low impedance connection to the processor I O power plane These signals must be connected to the voltage regulator feedback circuit which insures the output voltage that is processor voltage remains...

Страница 49: ...llaneous signals Refer to Table 7 5 for further details Note The processor is capable of up to 8 0 GT s speeds 7 1 3 DMI2 PCI Express Signals The Direct Media Interface DMI2 Gen 2 sends and receives p...

Страница 50: ...on at lower core frequencies than the factory set maximum core frequency The processor core frequency is configured during reset by using values stored within the device during manufacturing The store...

Страница 51: ...n Table 7 5 7 1 8 1 Power and Ground Lands All VCC VCCPLL VSA VCCD VTTA and VTTD lands must be connected to their respective processor power planes while all VSS lands must be connected to the system...

Страница 52: ...e calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings The processor uses voltage identification signals to support automa...

Страница 53: ...own transitions The VR does not control the slew rate the output voltage declines with the output load current only The SetVID Decay command is preemptive that is the VR interrupts its current process...

Страница 54: ...Rail Addressing The processor addresses 4 different voltage rail control segments within VR12 VCC VCCD_01 VCCD_23 and VSA The SVID data packet contains a 4 bit addressing code Notes 1 Check with VR v...

Страница 55: ...85 0 91000 A8 1 08500 CB 1 26000 EE 1 43500 40 0 56500 63 0 74000 86 0 91500 A9 1 09000 CC 1 26500 EF 1 44000 41 0 57000 64 0 74500 87 0 92000 AA 1 09500 CD 1 27000 F0 1 44500 42 0 57500 65 0 75000 88...

Страница 56: ...sistor will also allow for system testability 7 2 Signal Group Summary Signals are grouped by buffer type and similar characteristics as listed in Table 7 4 The buffer type indicates which signaling t...

Страница 57: ...EFDQTX_C 01 23 Reference Input DDR_VREFDQRX_C 01 23 DDR 01 23 _RCOMP 2 0 DDR3 Data Signals2 Differential SSTL Input Output DDR 0 1 2 3 _DQS_D N P 08 00 Single ended SSTL Input Output DDR 0 1 2 3 _DQ 6...

Страница 58: ..._N CMOS1 05v Input Output PREQ_N Open Drain CMOS Input Output BPM_N 7 0 EAR_N CMOS1 05v Output PRDY_N Open Drain CMOS Output TDO Serial VID Interface SVID Signals Single ended CMOS1 05v Input SVIDALER...

Страница 59: ...pled at PWRGOOD assertion Power Other Signals Power Ground VCC VTTA VTTD VCCD_01 VCCD_23 VCCPLL VSA and VSS Sense Points VCC_SENSE VSS_VCC_SENSE VSS_VTTD_SENSE VTTD_SENSE VSA_SENSE VSS_VSA_SENSE Notes...

Страница 60: ...uld always be taken to avoid high static voltages or electric fields Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 7...

Страница 61: ...for older model oscilloscopes using a 1 5 pF maximum probe capacitance and 1 M minimum impedance The maximum length of the ground wire on the probe should be less than 5 mm to ensure external noise fr...

Страница 62: ...to all processors These specifications are based on pre silicon characterization and will be updated as further data becomes available 2 ICC_TDC Thermal Design Current is the sustained DC equivalent...

Страница 63: ...current load condition This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_...

Страница 64: ...e 0 43 VCCD V 2 3 VIH Input High Voltage 0 57 VCCD V 2 4 5 RON DDR3 Data Buffer On Resistance 21 31 6 Data ODT On Die Termination for Data Signals 45 90 55 110 8 Reference Clock Signals Command and Da...

Страница 65: ...affect VTTD min max specification 2 It is expected that the PECI driver will take into account the variance in the receiver input thresholds and consequently be able to drive its output within safe li...

Страница 66: ...r Vin between 0 and Vih Table 7 14 System Reference Clock BCLK 0 1 DC Specifications Symbol Parameter Signal Min Max Unit Figure Notes1 VBCLK_diff_ih Differential Input High Voltage Differential 0 150...

Страница 67: ...Signals PREQ_N TCK TDI TMS TRST_N 50 50 A IIL Input Leakage Current Signals BPM_N 7 0 TDO EAR_N RTEST 50 ohm 900 A IO Output Current Signal PRDY_N RTEST 500 ohm 1 50 1 50 mA Input Edge Rate Signals BP...

Страница 68: ...w Voltage Signal PWRGOOD 0 320 V 1 2 4 VIH_MIN Input High Voltage Signal PWRGOOD 0 640 V 1 2 4 VOL_CMOS1 05v Output Low Voltage 0 12 VTT V 1 2 VOH_CMOS1 05v Output High Voltage 0 88 VTT V 1 2 IIL_CMOS...

Страница 69: ...s Base Specification 2 0 and 1 0 7 5 3 3 Reset and Miscellaneous Signal DC Specifications For a power on Reset RESET_N must stay active for at least 3 5 milliseconds after VCC and BCLK have reached th...

Страница 70: ...Electrical Specifications 70 Datasheet Volume 1...

Страница 71: ...or Land Listing 8 Processor Land Listing This chapter provides sorted land list Table 8 1 is a listing of all processor lands ordered alphabetically by land name Table 8 2 is a listing of all processo...

Страница 72: ...SSTL O DDR0_CLK_DN 2 CE21 SSTL O DDR0_CLK_DN 3 CF22 SSTL O DDR0_CLK_DP 0 CH24 SSTL O DDR0_CLK_DP 1 CG23 SSTL O DDR0_CLK_DP 2 CG21 SSTL O DDR0_CLK_DP 3 CH22 SSTL O DDR0_CS_N 0 CN25 SSTL O DDR0_CS_N 1 C...

Страница 73: ...O DDR0_DQS_DP 08 CC17 SSTL I O DDR0_ECC 0 CE15 SSTL I O DDR0_ECC 1 CC15 SSTL I O DDR0_ECC 2 CH18 SSTL I O Table 8 1 Land Name Sheet 3 of 45 Land Name Land No Buffer Type Direction DDR0_ECC 3 CF18 SST...

Страница 74: ...L I O Table 8 1 Land Name Sheet 5 of 45 Land Name Land No Buffer Type Direction DDR1_DQ 40 DA33 SSTL I O DDR1_DQ 41 DD32 SSTL I O DDR1_DQ 42 DC35 SSTL I O DDR1_DQ 43 DA35 SSTL I O DDR1_DQ 44 DA31 SSTL...

Страница 75: ...O DDR2_CS_N 1 AE19 SSTL O Table 8 1 Land Name Sheet 7 of 45 Land Name Land No Buffer Type Direction DDR2_CS_N 4 AA19 SSTL O DDR2_CS_N 5 P18 SSTL O DDR2_DQ 00 T40 SSTL I O DDR2_DQ 01 V40 SSTL I O DDR2...

Страница 76: ...SSTL I O DDR2_ECC 2 Y26 SSTL I O DDR2_ECC 3 AB26 SSTL I O DDR2_ECC 4 AB30 SSTL I O DDR2_ECC 5 AD30 SSTL I O Table 8 1 Land Name Sheet 9 of 45 Land Name Land No Buffer Type Direction DDR2_ECC 6 W27 SS...

Страница 77: ..._DQ 42 J9 SSTL I O Table 8 1 Land Name Sheet 11 of 45 Land Name Land No Buffer Type Direction DDR3_DQ 43 L9 SSTL I O DDR3_DQ 44 K14 SSTL I O DDR3_DQ 45 M14 SSTL I O DDR3_DQ 46 K10 SSTL I O DDR3_DQ 47...

Страница 78: ...and Name Sheet 13 of 45 Land Name Land No Buffer Type Direction PE_RBIAS AH52 PCIEX3 I O PE_RBIAS_SENSE AF52 PCIEX3 I PE_VREF_CAP AJ43 PCIEX3 I O PE1A_RX_DN 0 E51 PCIEX3 I PE1A_RX_DN 1 F52 PCIEX3 I PE...

Страница 79: ...I PE2D_RX_DP 13 AP56 PCIEX3 I PE2D_RX_DP 14 AY58 PCIEX3 I Table 8 1 Land Name Sheet 15 of 45 Land Name Land No Buffer Type Direction PE2D_RX_DP 15 AY56 PCIEX3 I PE2D_TX_DN 12 AY50 PCIEX3 O PE2D_TX_DN...

Страница 80: ...X3 O PE3D_TX_DP 13 Y44 PCIEX3 O PE3D_TX_DP 14 AC43 PCIEX3 O PE3D_TX_DP 15 T44 PCIEX3 O PECI BJ47 PECI I O PMSYNC K52 CMOS I PRDY_N R53 CMOS O PREQ_N U53 CMOS I O PROC_SEL_N AH42 O PROCHOT_N BD52 ODCMO...

Страница 81: ...SVD BP54 RSVD BP56 RSVD BR43 RSVD BR47 RSVD BR49 Table 8 1 Land Name Sheet 19 of 45 Land Name Land No Buffer Type Direction RSVD BR51 RSVD BT44 RSVD BT58 RSVD BU43 RSVD BU53 RSVD BU55 RSVD BU57 RSVD B...

Страница 82: ...VD CK28 RSVD CK32 RSVD CK46 RSVD CK48 RSVD CK50 Table 8 1 Land Name Sheet 21 of 45 Land Name Land No Buffer Type Direction RSVD CK52 RSVD CK54 RSVD CK56 RSVD CL13 RSVD CL27 RSVD CL39 RSVD CL45 RSVD CL...

Страница 83: ...9 RSVD DA53 RSVD DA55 RSVD DA57 RSVD DB14 RSVD DB38 Table 8 1 Land Name Sheet 23 of 45 Land Name Land No Buffer Type Direction RSVD DB42 RSVD DB44 RSVD DB46 RSVD DB48 RSVD DB50 RSVD DB52 RSVD DB54 RSV...

Страница 84: ...5 Land Name Land No Buffer Type Direction TEST1 CW1 O TEST2 F2 O TEST3 D4 O TEST4 BA55 I TESTHI_AT50 AT50 CMOS I TESTHI_BF48 BF48 Open Drain I O TESTHI_BH48 BH48 Open Drain I O THERMTRIP_N BL47 ODCMOS...

Страница 85: ...C AY6 PWR VCC AY8 PWR VCC BA1 PWR VCC BA11 PWR Table 8 1 Land Name Sheet 27 of 45 Land Name Land No Buffer Type Direction VCC BA13 PWR VCC BA15 PWR VCC BA17 PWR VCC BA3 PWR VCC BA5 PWR VCC BA7 PWR VCC...

Страница 86: ...PWR VCC BR3 PWR VCC BR5 PWR Table 8 1 Land Name Sheet 29 of 45 Land Name Land No Buffer Type Direction VCC BR7 PWR VCC BR9 PWR VCC BT10 PWR VCC BT12 PWR VCC BT14 PWR VCC BT16 PWR VCC BT2 PWR VCC BT4...

Страница 87: ...7 PWR VCCD_23 N19 PWR VCCD_23 N21 PWR VCCD_23 N23 PWR VCCD_23 V16 PWR VCCD_23 V18 PWR VCCD_23 V20 PWR VCCD_23 V22 PWR VCCD_23 V24 PWR Table 8 1 Land Name Sheet 31 of 45 Land Name Land No Buffer Type D...

Страница 88: ...SS AG9 GND VSS AH58 GND VSS AJ15 GND VSS AJ17 GND Table 8 1 Land Name Sheet 33 of 45 Land Name Land No Buffer Type Direction VSS AK10 GND VSS AK12 GND VSS AK14 GND VSS AK16 GND VSS AK2 GND VSS AK4 GND...

Страница 89: ...8 GND VSS BE49 GND VSS BE51 GND VSS BF42 GND Table 8 1 Land Name Sheet 35 of 45 Land Name Land No Buffer Type Direction VSS BF44 GND VSS BG47 GND VSS BH58 GND VSS BJ55 GND VSS BJ57 GND VSS BK42 GND VS...

Страница 90: ...GND VSS CC47 GND VSS CC49 GND VSS CC9 GND Table 8 1 Land Name Sheet 37 of 45 Land Name Land No Buffer Type Direction VSS CD18 GND VSS CD36 GND VSS CD6 GND VSS CE13 GND VSS CE5 GND VSS CE9 GND VSS CF12...

Страница 91: ...CP48 GND VSS CP50 GND VSS CP52 GND VSS CP56 GND Table 8 1 Land Name Sheet 39 of 45 Land Name Land No Buffer Type Direction VSS CR11 GND VSS CR35 GND VSS CR47 GND VSS CR49 GND VSS CR5 GND VSS CR9 GND V...

Страница 92: ...GND VSS DF48 GND VSS DF50 GND VSS DF52 GND VSS DF8 GND VSS E1 GND Table 8 1 Land Name Sheet 41 of 45 Land Name Land No Buffer Type Direction VSS E29 GND VSS E3 GND VSS E31 GND VSS E41 GND VSS E5 GND V...

Страница 93: ...R39 GND VSS R5 GND VSS R55 GND Table 8 1 Land Name Sheet 43 of 45 Land Name Land No Buffer Type Direction VSS R7 GND VSS T28 GND VSS T4 GND VSS T42 GND VSS T6 GND VSS T8 GND VSS U35 GND VSS U5 GND VSS...

Страница 94: ...9 PWR VTTA Y54 PWR VTTD AF22 PWR VTTD AF24 PWR VTTD AG21 PWR VTTD AG23 PWR VTTD AM42 PWR VTTD AT42 PWR VTTD AY42 PWR VTTD BD42 PWR VTTD BH42 PWR VTTD BK56 PWR VTTD BL51 PWR VTTD BM42 PWR VTTD BR55 PWR...

Страница 95: ...X3 O AA49 PE3A_RX_DP 3 PCIEX3 I AA5 VSS GND AA51 PE3B_RX_DP 7 PCIEX3 I AA53 PE3B_RX_DP 6 PCIEX3 I AA55 VSS GND AA7 RSVD AA9 VSS GND AB10 DDR2_DQ 38 SSTL I O AB12 RSVD AB14 VSS GND AB16 RSVD AB18 DDR2_...

Страница 96: ...E17 VSA PWR AE19 DDR2_CS_N 1 SSTL O AE21 RSVD Table 8 2 Land Number Sheet 3 of 45 Land No Land Name Buffer Type Direction AE23 RSVD AE25 RSVD AE27 DDR_RESET_C23_N CMOS1 5v O AE29 VSS GND AE3 DDR2_DQ 6...

Страница 97: ...2 PCIEX3 I AH48 PE3C_RX_DN 8 PCIEX3 I Table 8 2 Land Number Sheet 5 of 45 Land No Land Name Buffer Type Direction AH50 PE3C_RX_DN 10 PCIEX3 I AH52 PE_RBIAS PCIEX3 I O AH54 PE2B_TX_DP 5 PCIEX3 O AH56...

Страница 98: ...6 PCIEX3 O AN55 VSS GND AN57 VSS GND Table 8 2 Land Number Sheet 7 of 45 Land No Land Name Buffer Type Direction AN7 VCC PWR AN9 VCC PWR AP10 VCC PWR AP12 VCC PWR AP14 VCC PWR AP16 VCC PWR AP2 VCC PW...

Страница 99: ...r Sheet 9 of 45 Land No Land Name Buffer Type Direction AW15 VCC PWR AW17 VCC PWR AW3 VCC PWR AW43 BPM_N 5 ODCMOS I O AW45 BCLK1_DP CMOS I AW47 PE2D_TX_DP 15 PCIEX3 O AW49 PE2D_TX_DP 13 PCIEX3 O AW5 V...

Страница 100: ...4 PE2C_TX_DN 10 PCIEX3 O BB56 PE2D_RX_DN 15 PCIEX3 I BB58 VSS GND BB6 VCC PWR BB8 VCC PWR BC1 VSS GND BC11 VSS GND BC13 VSS GND Table 8 2 Land Number Sheet 11 of 45 Land No Land Name Buffer Type Direc...

Страница 101: ...VCC PWR BH42 VTTD PWR BH44 RSVD Table 8 2 Land Number Sheet 13 of 45 Land No Land Name Buffer Type Direction BH46 RSVD BH48 TESTHI_BH48 Open Drain I O BH50 RSVD BH52 RSVD BH54 RSVD BH56 RSVD BH58 VSS...

Страница 102: ...VD BN5 VCC PWR BN51 RSVD BN53 RSVD Table 8 2 Land Number Sheet 15 of 45 Land No Land Name Buffer Type Direction BN55 RSVD BN57 RSVD BN7 VCC PWR BN9 VCC PWR BP10 VCC PWR BP12 VCC PWR BP14 VCC PWR BP16...

Страница 103: ...S GND Table 8 2 Land Number Sheet 17 of 45 Land No Land Name Buffer Type Direction BW11 VSS GND BW13 VSS GND BW15 VSS GND BW17 VSS GND BW3 VCC_SENSE O BW43 TDI CMOS I BW45 RSVD BW47 RSVD BW49 RSVD BW5...

Страница 104: ...CMOS O CA45 RSVD CA47 RSVD Table 8 2 Land Number Sheet 19 of 45 Land No Land Name Buffer Type Direction CA49 RSVD CA5 VSS GND CA51 RSVD CA53 VTTA PWR CA55 VSS GND CA57 VSS GND CA7 DDR0_DQ 05 SSTL I O...

Страница 105: ...CD8 DDR0_DQ 01 SSTL I O Table 8 2 Land Number Sheet 21 of 45 Land No Land Name Buffer Type Direction CE11 DDR0_DQS_DP 03 SSTL I O CE13 VSS GND CE15 DDR0_ECC 0 SSTL I O CE17 DDR0_DQS_DN 08 SSTL I O CE1...

Страница 106: ...L O CH26 DDR0_CS_N 1 SSTL O Table 8 2 Land Number Sheet 23 of 45 Land No Land Name Buffer Type Direction CH28 DDR0_ODT 2 SSTL O CH30 DDR0_DQ 45 SSTL I O CH32 RSVD CH34 DDR0_DQ 47 SSTL I O CH36 VSS GND...

Страница 107: ...O CL33 DDR0_DQS_DN 05 SSTL I O CL35 DDR0_DQ 42 SSTL I O CL37 DDR0_DQ 61 SSTL I O CL39 RSVD CL41 DDR0_DQ 63 SSTL I O CL43 VSS GND Table 8 2 Land Number Sheet 25 of 45 Land No Land Name Buffer Type Dir...

Страница 108: ...le 8 2 Land Number Sheet 27 of 45 Land No Land Name Buffer Type Direction CP58 RSVD CP6 DDR1_DQ 20 SSTL I O CP8 RSVD CR1 RSVD CR11 VSS GND CR13 DDR1_DQ 24 SSTL I O CR15 DDR1_DQS_DN 03 SSTL I O CR17 DD...

Страница 109: ...DQ 17 SSTL I O CU9 DDR1_DQS_DP 02 SSTL I O Table 8 2 Land Number Sheet 29 of 45 Land No Land Name Buffer Type Direction CV10 DDR1_DQ 23 SSTL I O CV12 DDR1_DQ 29 SSTL I O CV14 VSS GND CV16 DDR1_DQ 31 S...

Страница 110: ...nd Number Sheet 31 of 45 Land No Land Name Buffer Type Direction D16 RSVD D18 DDR3_MA 10 SSTL O D2 VSS GND D20 DDR3_MA 04 SSTL O D22 DDR3_MA 08 SSTL O D24 DDR3_MA 14 SSTL O D26 VSS GND D32 DDR3_DQ 18...

Страница 111: ...O DC23 DDR1_MA 00 SSTL O DC25 DDR1_BA 1 SSTL O DC3 VSS GND DC33 RSVD Table 8 2 Land Number Sheet 33 of 45 Land No Land Name Buffer Type Direction DC35 DDR1_DQ 42 SSTL I O DC37 DDR1_DQ 61 SSTL I O DC39...

Страница 112: ...DDR3_DQS_DP 08 SSTL I O E29 VSS GND Table 8 2 Land Number Sheet 35 of 45 Land No Land Name Buffer Type Direction E3 VSS GND E31 VSS GND E33 DDR3_DQS_DP 02 SSTL I O E35 DDR3_DQ 20 SSTL I O E37 DDR3_DQ...

Страница 113: ...and Name Buffer Type Direction H36 DDR3_DQ 15 SSTL I O H38 VSS GND H4 DDR3_DQ 61 SSTL I O H40 VSS GND H42 PE1A_TX_DP 0 PCIEX3 O H44 PE1A_TX_DP 2 PCIEX3 O H46 PE1B_TX_DP 4 PCIEX3 O H48 PE1B_TX_DP 6 PCI...

Страница 114: ...STL I O L35 DDR3_DQ 10 SSTL I O L37 DDR3_DQS_DN 01 SSTL I O L39 DDR3_DQ 09 SSTL I O Table 8 2 Land Number Sheet 39 of 45 Land No Land Name Buffer Type Direction L41 VSS GND L43 PE1A_TX_DN 1 PCIEX3 O L...

Страница 115: ...IEX3 O P52 PE3B_TX_DP 4 PCIEX3 O Table 8 2 Land Number Sheet 41 of 45 Land No Land Name Buffer Type Direction P54 VSS GND P56 VSS GND P6 DDR3_DQ 51 SSTL I O P8 VSS GND R11 VSS GND R13 DDR2_DQ 48 SSTL...

Страница 116: ...U55 PE2A_RX_DP 3 PCIEX3 I U7 DDR2_DQ 44 SSTL I O U9 DDR2_DQ 55 SSTL I O V10 DDR2_DQ 51 SSTL I O V12 RSVD V14 DDR2_DQ 53 SSTL I O V16 VCCD_23 PWR V18 VCCD_23 PWR Table 8 2 Land Number Sheet 43 of 45 L...

Страница 117: ..._CLK_DN 1 SSTL O Y24 DDR2_CLK_DN 0 SSTL O Y26 DDR2_ECC 2 SSTL I O Y28 VSS GND Y30 VSS GND Y32 VSS GND Y34 RSVD Y36 VSS GND Y38 VSS GND Y4 DDR2_DQ 57 SSTL I O Y40 VSS GND Y42 VSS GND Y44 PE3D_TX_DP 13...

Страница 118: ...Processor Land Listing 118 Datasheet Volume 1...

Страница 119: ...Mechanical Specifications 9 Package Mechanical Specifications For mechanical specifications and design guidelines refer to the Intel Core i7 Processor Family for the LGA 2011 Socket Thermal Mechanical...

Страница 120: ...Package Mechanical Specifications 120 Datasheet Volume 1...

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