TERMINAL DESCRIPTION(5/10)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -47
Q8200: FLI30336 (Video Processor, TORINO)
TX-SR806/SA806
OCM External ROM/SRAM Control Signal
O
I/O
I/O
I/O
O
O
Chip select output signal to external ROM.
Chip select output signal to external peripheral.
Chip select output signal to external peripheral.
Chip select output signal to external peripheral.
Read enable output signal to enable external device to drive data pin(ball).
Write enable output signal to enable writing external devices.
ROM_CSn
OCM_CS0n
OCM_CS1n
OCM_CS2n
OCM_REn
OCM_WEn
AD24
AD25
AD26
AC24
AC25
AC26
Pin name Pin# I/O Description
OCM Peripherals
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Interrupt #1 input for generating system interrupt to OCM. Level sensitive.
Interrupt #2 input for generating system interrupt to OCM. Edge sensitive.
OCM UART ‘0’ data output.
OCM UART ‘0’ data input.
OCM UART ‘1’ data output.
OCM UART ‘1’ data input.
Input to IR decoder.
Pulse width modulator ‘0’ output.
Pulse width modulator ‘1’ output.
Pulse width modulator ‘2’ output.
Timer In: used as clock or clock enable input to OCMTIMER1.
Two wire serial master - Bus ‘0’ data.
Two wire serial master - Bus ‘0’ data.
Two wire serial master - Bus ‘1’ data.
Two wire serial master - Bus ‘1’ data.
Two wire serial master - Bus ‘2’ data.
Two wire serial master - Bus ‘2’ data.
Can be configured as data for two wire serial In-Circuit JTAG debugger.
Can be configured as clock for two wire serial In-Circuit JTAG debugger.
Can be configured as data for two wire serial In-Circuit JTAG debugger.
Can be configured as clock for two wire serial In-Circuit JTAG debugger.
Two wire slave serial data.
Two wire slave serial clock.
OCM_INT1
OCM_INT2
OCM_UDO_0
OCM_UDI_0
OCM_UDO_1
OCM_UDI_1
IR0
PWM0
PWM1
PWM2
OCM_TIMER1
MSTR0_SDA
MSTR0_SCL
MSTR1_SDA
MSTR1_SCL
MSTR2_SDA
MSTR2_SCL
VGA0_SDA
W23
Y24
W26
W25
B2
B3
AB24
V24
U23
U24
W24
AA23
AA24
A2
A3
AB25
AB26
AA25
AA26
Y25
Y26
V25
V26
Pin name Pin# I/O Description
I/O
I/O
Hard Reset, active low input.
No connect.
AD9
A1
Power Panel Control
O
O
Panel Power Control output controlled by Panel Power On Sequencer.
Panel Bias Control controlled by Panel Power On Sequencer.
PPWR
PBIAS
U25
U26
Pin name Pin# I/O Description
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