TERMINAL DESCRIPTION(5/5)
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -21
Q3401, Q3501: D790E001BZDH300 (Audio DSP)
TX-SR806/SA806
BALL
SIGNAL NAME
TYPE
(1)
PULL
(2)
GPIO
(3)
DESCRIPTION
NO.
McASP0, McASP1, McASP2, and SPI1 Serial Ports
AHCLKR0/AHCLKR1
B3
IO
-
Y
McASP0 and McASP1 Receive Master Clock
ACLKR0
A5
IO
-
Y
McASP0 Receive Bit Clock
AFSR0
B4
IO
-
Y
McASP0 Receive Frame Sync (L/R Clock)
AHCLKX0/AHCLKX2
C2
IO
-
Y
McASP0 and McASP2 Transmit Master Clock
ACLKX0
A4
IO
-
Y
McASP0 Transmit Bit Clock
AFSX0
A3
IO
-
Y
McASP0 Transmit Frame Sync (L/R Clock)
AMUTE0
C1
O
-
Y
McASP0 MUTE Output
AXR0[0]
A14
IO
-
Y
McASP0 Serial Data 0
AXR0[1]
B13
IO
-
Y
McASP0 Serial Data 1
AXR0[2]
A13
IO
-
Y
McASP0 Serial Data 2
AXR0[3]
B12
IO
-
Y
McASP0 Serial Data 3
AXR0[4]
A12
IO
-
Y
McASP0 Serial Data 4
AXR0[5]/SPI1_SCS
B11
IO
-
Y
McASP0 Serial Data 5
or
SPI1 Slave Chip Select
AXR0[6]/SPI1_ENA
A11
IO
-
Y
McASP0 Serial Data 6
or
SPI1 Enable (Ready)
AXR0[7]/SPI1_CLK
B10
IO
-
Y
McASP0 Serial Data 7
or
SPI1 Serial Clock
AXR0[8]/AXR1[5]/
McASP0 Serial Data 8
or
McASP1 Serial Data 5
or
B9
IO
-
Y
SPI1_SOMI
SPI1 Data Pin Slave Out Master In
AXR0[9]/AXR1[4]/
McASP0 Serial Data 9
or
McASP1 Serial Data 4
or
A9
IO
-
Y
SPI1_SIMO
SPI1 Data Pin Slave In Master Out
AXR0[10]/AXR1[3]
B8
IO
-
Y
McASP0 Serial Data 10
or
McASP1 Serial Data 3
AXR0[11]/AXR1[2]
A8
IO
-
Y
McASP0 Serial Data 11
or
McASP1 Serial Data 2
AXR0[12]/AXR1[1]
B7
IO
-
Y
McASP0 Serial Data 12
or
McASP1 Serial Data 1
AXR0[13]/AXR1[0]
B6
IO
-
Y
McASP0 Serial Data 13
or
McASP1 Serial Data 0
AXR0[14]/AXR2[1]
A6
IO
-
Y
McASP0 Serial Data 14
or
McASP2 Serial Data 1
AXR0[15]/AXR2[0]
B5
IO
-
Y
McASP0 Serial Data 15
or
McASP2 Serial Data 0
ACLKR1
E1
IO
-
Y
McASP1 Receive Bit Clock
AFSR1
F1
IO
-
Y
McASP1 Receive Frame Sync (L/R Clock)
D1
IO
-
Y
McASP1 Transmit Master Clock
E2
IO
-
Y
McASP1 Transmit Bit Clock
F2
IO
-
Y
McASP1 Transmit Frame Sync (L/R Clock)
D2
O
-
Y
McASP1 MUTE Output
C14
IO
IPD
Y
McASP2 Receive Master Clock
C13
IO
IPD
Y
McASP2 Receive Bit Clock
C12
IO
IPD
Y
McASP2 Receive Frame Sync (L/R Clock)
D11
IO
IPD
Y
McASP2 Transmit Bit Clock
C11
IO
IPD
Y
McASP2 Transmit Frame Sync (L/R Clock)
AMUTE2/HINT
D10
O
IPD
Y
McASP2 MUTE Output
or
UHPI Host Interrupt
SPI0, I2C0, and I2C1 Serial Port Pins
SPI0_SOMI/I2C0_SDA
B14
IO
-
Y
SPI0 Data Pin Slave Out Master In
or
I2C0 Serial Data
SPI0_SIMO
B15
IO
-
Y
SPI0 Data Pin Slave In Master Out
SPI0_CLK/I2C0_SCL
C16
IO
-
Y
SPI0 Serial Clock
or
I2C0 Serial Clock
SPI0_SCS/I2C1_SCL
C15
IO
-
Y
SPI0 Slave Chip Select
or
I2C1 Serial Clock
SPI0_ENA/I2C1_SDA
D16
IO
-
Y
SPI0 Enable (Ready)
or
I2C1 Serial Data
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