BLOCK DIAGRAM
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -41
Q8200: FLI30336 (Video Processor, TORINO)
TX-SR806/SA806
IPCLK0
IPCLK1
IPCLK2
IPCLK3
DIP
CLK
MUX
DIP_PIP_CLK
DIP_MAIN_CLK
DIG_PORTA[23:0]
AODD
AHSYNC
AVSYNC
DIG_PORTB[23:0]
BODD
BHSYNC
BVSYNC
AHS_CS_RAW
AEXT_CLAMP
AEXT_COAST
DIP_CSYNC
HS
VS
P
o
rt
Configur
ation
Port
Select
PIP
Bus
Swap
MAIN
Bus
Swap
PIP
Bus
Flip
MAIN
Bus
Flip
656
Decoder
656
Decoder
A1
A2
A3
A4
A_RETUR
B1
B2
B3
B4
B_RETUR
C1
C2
C3
C4
C_RETUR
SV1
SV2
SV3
SV4
SV_RETUR
Analog Mux
VOUT
V1_
ADC A
V1_
ADC B
V1_
ADC C
V1_Sync
ADC
V1_Sync
Slicer
V2_
ADC A
V2_
ADC B
V2_
ADC C
V2_Sync
ADC
V2_Sync
Slicer
Sync
Processor
Sync
Processor
V1_Decimation
Filter
V2_Decimation
Filter
V2_Decimation
Filter
V2_Decimation
Filter
V1_Decimation
Filter
V1_Decimation
Filter
3D Video
Decoder
VBI Slicer
SCART
Overlay
Input
Select
Mux
IWC
RGB2YUV
RGB2YUV
4:4:4-4:2:2
4:4:4-4:2:2
Neas
Win
Neas
Win
PXL
Grab
PXL
Grab
IBD
Sum
Diff
Feat
Det
IBD
Sum
Diff
Feat
Det
LTR
Box
WSS
WSS
MAIN
IFM
IFM3
PIP
IFM
DCDi
Vertical Scaler
DCDi
MADi
Vertical Scaler
Peaking Filter
Peaking Filter
Peaking Filter
Peaking Filter
to MC
from MC
PIP Vertical Filter(PVF)
PIP Horizontal Filter(PHF)
Main Horizontal Filter(PHF)
MAIN Channel
IVP
CCS
TNR+
3:2
Pull
Down
+
Input Main Processor(IMP)
Main Vertical Filter(MVF)
Horizontal
Scaler
Horizontal
Scaler
PIP Channel Data Router
Main Channel Data Router
MPEG
Noise
Reduction
Output Display
Processor
4:2:2-4:4:4
4:2:2-4:4:4
3x3 Matrix
PIP/MAIN
Blender
Multipip
Engine
Video LUT
Gamma
Dither
Response Time Enhancement
OSD
Blender
OSD CTRL
HW Engine
LVDS
Interface
LVDS
Mapping
TTL
Interface
Panel
Power
CTRL
Master
Slave Sync
PXL
Grab
Display Engine
Display
Timing
Generator
I2S
Controller
Arbiter
Address Generator
FRC Controller
DDR Memory Interface
Memory Controller(MC)
Dynamic Scaler
Controller
On Chip Microcontroller(OCM)
Turbo186
JTAG
Code
Patch
FS Bridge
Table Access
Bridge
64K ROM
64K SRAM
Low Band Width
ADC
I2C
Master
I2C
ddc2bi
I2C
Slave
ddc2bi
JTAG
Bridge
Ext
RAM/ROM
I/F
Update
Controller
IRQ Controller
Reset
Controller
Host
Register
Interface
PWM
GPIO
IR
x186 Bus
JTAG Boundary
Scan
OSC
iAVS_CLK
TCLK
SCLK2
ECLK2
SCLK
ECLK
OCLK
FCLK
DCLK
SDDS2
SDDS
EDDS2
EDDS
ODDS
FDDS
DDDS
RCLK
TCLK
RCLK
PLL
19.6608MHz
Bootstrap
Clock Gen
Input PIP Processor(IPP)
Digital Input Port(DIP)
PIP Channel
Edge
Enhancement
RGB2YUV
ACC+
ACM-3D
(Blue Stretch)
3x3 Matrix
TPG
TPG
DWORD Co-processor
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299