Everest CORE - Product Manual |
Application Guide
INGENIA | 08/01/2019
47
Signal
Description
DIG_ENC_B_
N
DIG_ENC_Z_P Incremental encoder Index differential pair
DIG_ENC_Z_N
GND_D
Logic supply reference voltage. To be connected to pin 22 of Everest CORE Feedback connector
whenever Digital Encoder 1 is wired. Connect to pin 36 of Everest CORE Feedback connector if
Digital Encoder 2 is wired
Design Notes
•
Resistors R3, R9 and R15 are termination resistors. 120
Ω
could also be used in case of a harsh
electromagnetic environment.
•
C3, C4, C6, C7, C9 and C10, in combination with R4, R5, R10, R11, R16 and R17, perform a protective function
of the transceiver in front of spikes or ESD, and at the same time increases immunity to common mode
noise. Capacitors could be increased up to 220 pF to reinforce this effects even more if required.
•
C2, C5 and C8 are decoupling capacitors for U1, U2 and U3.
•
To interface a single-ended encoder, connect the ABZ signals to the positive terminal of each differential
pair and leave the negative unconnected. It is mandatory that the encoder and the Everest CORE then share
their reference voltage or Ground.
Bill of materials
Designator
Part Number
Manufactur
er
Packag
e
Value / Description
C1, C2, C5, C8
GRM155R71C104KA
88D
Murata
0402
Ceramic capacitor, 100 nF, 16 V, X7R
C3, C4, C6, C7, C9, C10
CC0402JRNPO9BN1
01
Yageo
0402
Ceramic capacitor, 100 pF, 50 V, NP0
R1, R2, R6, R7, R8, R12,
R13, R14, R18
RMCF0402FT2K00
Stackpole
0402
Thick film resistor, 2 k
Ω
, 1 %
tolerance, 1/16 W
R3, R9, R15
ERJ3EKF2200V
Panasonic
0603
Thick film resistor, 220
Ω
, 1 %
tolerance, 0.1 W
R4, R5, R10, R11, R16,
R17
MC 0.063W 0603 1%
10R
Multicomp
0603
Thick film resistor, 10
Ω
, 1 %
tolerance, 1/16 W
U1, U2, U3
MAX3T
Maxim
SOT-23-
5N
Single differential RS422/RS485 line
receiver, 52 Mbps, 3 V to 5.5 V supply
Absolute Encoder
This circuit is designed to set a RS422/485-based physical layer, which is the most common among absolute
encoders. It sets 2 half-duplex channels, one for the "clock" signal, which is always a transmitter driven from the
Everest CORE, and the other for the "data" signal, which is always a receiver. With this, Everest CORE will be able to
interface most
SSI or BISS-C absolute encoders available.