Infineon CY8CKIT-041S-MAX, Руководство пользователя

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User Guide 14 of 56 002-32436 Rev. *B
<2021-06>
CY8CKIT-041S- MAX PSoC™ 4100S Max pioneer kit guide
Kit operation
2 Kit operation
This chapter introduces you to various feature of PSoC ™ 4100S Max pioneer kit including the theory of
operation and the onboard KitProg3 programming and debugging functionality, USB-UART, and USB-I2C
bridges.
2.1 Theory of operation
The PSoC ™ 4100S Max pioneer board is built around a PSoC ™ 4100S Max MCU. Figure 3 shows the block
diagram of the PSoC ™ 4100S Max MCU device used on the board. For details of device features, see the device
datasheet .
Peripherals
CPU Subsystem
System Interconnect (Single Layer AHB)
PSoC 4100S
Max
IO
SS
G
PI
O
(13
x ports)
I/O Subsystem
Peripheral Interconnect (MMIO)
PCLK
FLASH
384 KB
Read Accelerator
SPCIF
32-bit
AHB-Lite
Up to 84x GPIOs
Deep Sleep
Active/Sleep
Power Modes
Digital DFT
Test
Analog DFT
System Resources
Lite
Power
Clock
Reset
Clock Control
IMO
Sleep Control
REF POR
Reset Control
TestMode Entry
WIC
XRES
WDT
ILO
PWRSYS
8
x
T
C
P
W
M
W
C
O
2
x
L
P
C
o
m
p
a
ra
to
r
SAR ADC
(12-bit)
x1
1x CTBm
2x Opamp
Programmable
Analog
SARMUX
High Speed I/O Matrix and 3x Smart I/O
SWD/TC, MTB
NVIC, IRQMUX, MPU
Cortex
M0+
48 MHz
FAST MUL
L
C
D
2
x
C
a
p
S
e
n
se
E
X
C
O
(
w
P
L
L
)
C
A
N
F
D
DataWire/
DMA
Initiator/MMIO
C
R
Y
P
T
O
(AES,
SH
A,
T
R
N
G
,
PR
N
G
,
C
R
C
)
I2
S
M
a
st
e
r
T
X
5
x
S
C
B
-
I2C/SPI/UART
ROM
8 KB
ROM Controller
SRAM
32 KB
SRAM Controller
Figure 3 PSoC ™ 4100S Max MCU block diagram