Infineon C166 Series, Примечание к применению

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AP29000
Connecting C166 and C500 Microcontroller to CAN
The Infineon CAN Devices C167CR, C515C and SAE 81C90/91
Application Note 24 V 1.0, 2004-02
The second block of the CAN module on the C167CR and the C515C is the CAN
controller itself, which is derived from the stand-alone component AN 82527. The CAN
controller provides all resources that are required to run the Standard CAN protocol
(11-bit identifiers) as well as the Extended CAN protocol (29-bit identifiers). It provides
a sophisticated object layer to relieve the CPU of as much overhead as possible when
controlling many different message objects (up to 15). This includes bus arbitration,
resending of garbled messages, error handling, interrupt generation, etc. In order to
implement the physical layer, external CAN transceiver components have to be
connected to the C167CR / C515C.
The CAN controller combines several functional blocks (see figure 3.2-2) that work in
parallel and contribute to the controller’s performance. These units and the functions
they provide are described below.
•
The Transmit / Receive Shift Register holds the destuffed bit stream from the bus
line to allow the parallel access to the whole data or Remote Frame for the
acceptance match test and the parallel transfer of the frame to and from the
Intelligent Memory.
•
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data
stream between the Tx/Rx Shift Register, the CRC Register, and the bus line. The
BSP also controls the Error Management Logic (EML) and the parallel data stream
between the Tx/Rx Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed
according to the CAN protocol. Note that the automatic retransmission of messages
which have been corrupted by noise or other external error conditions on the bus
line is handled by the BSP.
•
The Cyclic Redundancy Check Register generates the Cyclic Redundancy Check
(CRC) code to be transmitted after the data bytes and checks the CRC code of
incoming messages. This is done by dividing the data stream by the code generator
polynomial.
•
The Error Management Logic (EML) is responsible for the fault confinement of the
CAN device. Its counters, the Receive Error Counter and the Transmit Error
Counter, are incremented and decremented by commands from the Bit Stream
Processor. According to the values of the error counters, the CAN controller is set
into the states
error active , error passive or busoff .
•
The CAN controller is error active , if both error counters are below the error passive
limit of 128. It is error passive , if at least one of the error counters equals or exceeds
128. It goes busoff , if the Transmit Error Counter equals or exceeds the busoff limit
of 256. The device remains in this state, until the busoff recovery sequence is
finished. Additionally, there is the bit EWRN in the Status Register, which is set, if at
least one of the error counters equals or exceeds the error warning limit of 96.
EWRN is reset if both error counters are less than the error warning limit.