IPX Manual RB01
3.5
IPX-VGA REGISTERS
3.5.1
IPX-VGA Control Registers
BOOT CONTROL:
A
ss FF
ory def
alue 0x
D7 D6 D5 D4
D3
D2 D
ddre
, fact
ault v
00.
1
D0
0
0
0
0
0
0
0
Boot Mode
Table 3.3. IPX-VGA Boot Control Register.
1:
CAMERA CONTROL
Add
0x00,
ry defa
alue 0x
ress
facto
ult v
02.
D7
D6 D5 D4 D3 D2 D1 D0
Horizontal
W
enable
Integration
enable
enable
W
enable
Binning
enable
enable
enable
enable
indow
Long
Shutter
Vertical
indow
Vertical
Mirror
Image
Dual
Out
Strobe
Table 3.4. IPX-VGA Camera Control 1 Register.
2:
CAMERA CONTROL
Address 0x01, factory default value 0x00.
D7
D6
D5
D4
D3
D2
D1
D0
8/10/12
bits 0
Test
Mode 1
Mode 0
enable
8/10/12
bits 1
Horizontal
enable
enable
enable
Test
Gamma
Binning
CC1
Trigger
External
Trigger
Table 3.5. IPX-VGA Camera Control 2 Register.
0 - disable
1 - enable
0 – Boot from Factory settings
1 – Boot from User settings
0 - disable
1 - enable
00 - disable
01 - fixed image #1
10 - fixed image #2
11 - moving image
00 – 8 bit
01 – 10 bit
10 – 12 bit
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85
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Содержание IPX CAMERA SERIES
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