PORT 3
1-2 : HOT-PLUG
(DEFAULT)
2-3 : PC PWR
1-2 : HOT-PLUG
(DEFAULT)
2-3 : PC PWR
LABEL:
PORT 2
PCIE X4 (1)
PCIE X4 (1)
LABEL:
Thu Jul 26 15:56:15 2007
SHEET 15 OF 17
1.0
18-637-001
D.Huang
2007
J.Carrillo
STGSCH-00117
89EBPES4T4
Evaluation
Board
B
R196
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J9
R209
C106
C107
C118
C119
R199
W31
W30
W32
C120
C121
C122
C123
W35
W34
W33
R190
W7
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J14
W6
R193
0
PORT 2 AND PORT 3
10UF
5.1K
9
9
8
S2_WAKEN
12
15
4
14
4
14
14
7
5
12
15
16
15
14
12
5
12
15
16
15
8
11
11
11
10
10
10
14
14
4
4
15
7
14
14
P3RSTN
0%
108051-301AC
5%
25V
10UF
25V
10UF
25V
25V
10UF
0
0%
25V
10UF
25V
10UF
25V
10UF
25V
10UF
2.7K
5%
108051-301AC
5%
5.1K
S3_RSTN
S3_REFCLKP
S3_PERP0
S3_REFCLKN
S3_PETN0
S3_PETP0
S3_WAKEN
U_PERSTN
S3_RSTN
S3_PERN0
P2RSTN
U_PERSTN
S2_RSTN
P3PRDETN
S3_12V
S3_3VAUX
S3_3V
S2_3V
S2_12V
S2_3VAUX
S2_PERN0
S2_PERP0
S2_REFCLKN
S2_REFCLKP
S2_RSTN
P2PRDETN
S2_PETN0
S2_PETP0
TITLE
DRAWING
NO.
AUTHOR
CHECKED
BY
COPYRIGHT (C) IDT
3
SIZE
REV.
FAB P/N
1
1
A
A
B
B
C
C
D
D
2
2
4
4
5
6
6
7
7
8
3
8
5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL
PROPERTY OF INTEGRATED
DEVICE TECHNOLOGY,
INC.
OUT
OUT
IN
IN
3_3V
PCIE_CONN_x4_OPEN_SLOT
GND
REFCLK-
RSVD
GND
PERP1
GND
GND
PERN2
3.3VAUX
RSVD
GND
PETN1
PRSTN2#
GND
RSVD
GND
PETN3
GND
GND
PETP3
PETN2
PETP2
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
+3.3V
GND
+3.3V
+12V
+12V
JTAG3
JTAG4
JTAG5
PERST#
GND
PERP0
GND
PERN0
RSVD
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
JTAG1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
GND
GND
PRSTN1#
+12V
WAKE#
JTAG2
OUT
OUT
IN
IN
IN
3_3V
IN
IN
IN
IN
3_3V
12_0V
3_3V
IN
IN
3_3V
IN
IN
OUT
3_3V
IN
12_0V
3_3V
OUT
IN
IN
OUT
PCIE_CONN_x4_OPEN_SLOT
GND
REFCLK-
RSVD
GND
PERP1
GND
GND
PERN2
3.3VAUX
RSVD
GND
PETN1
PRSTN2#
GND
RSVD
GND
PETN3
GND
GND
PETP3
PETN2
PETP2
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
+3.3V
GND
+3.3V
+12V
+12V
JTAG3
JTAG4
JTAG5
PERST#
GND
PERP0
GND
PERN0
RSVD
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
JTAG1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
GND
GND
PRSTN1#
+12V
WAKE#
JTAG2
IN
IN
OUT
OUT
IN
IN
OUT
Содержание EB4T4 Eval Board
Страница 4: ...IDT Table of Contents EB4T4 Eval Board Manual ii August 20 2007 Notes...
Страница 6: ...IDT List of Tables EB4T4 Eval Board Manual iv August 20 2007 Notes...
Страница 8: ...IDT List of Figures EB4T4 Eval Board Manual vi August 20 2007 Notes...
Страница 24: ...IDT Software for the EB4T4 Eval Board EB4T4 Eval Board Manual 3 2 August 20 2007 Notes...
Страница 25: ...Notes EB4T4 Eval Board Manual 4 1 August 20 2007 Chapter 4 Schematics Schematics...