IDT Installation of the EB4T4 Eval Board
EB4T4 Eval Board Manual
2 - 4
August 20, 2007
Notes
Figure 2.3 APWRDIS# Timing
On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it
must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will
not affect the APWRDIS# state. This timing will be provided by the following circuit.
Figure 2.4 APWRDIS# Timing Circuit
Содержание EB4T4 Eval Board
Страница 4: ...IDT Table of Contents EB4T4 Eval Board Manual ii August 20 2007 Notes...
Страница 6: ...IDT List of Tables EB4T4 Eval Board Manual iv August 20 2007 Notes...
Страница 8: ...IDT List of Figures EB4T4 Eval Board Manual vi August 20 2007 Notes...
Страница 24: ...IDT Software for the EB4T4 Eval Board EB4T4 Eval Board Manual 3 2 August 20 2007 Notes...
Страница 25: ...Notes EB4T4 Eval Board Manual 4 1 August 20 2007 Chapter 4 Schematics Schematics...