IDT CPS Registers
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
10 - 37
July 10, 2012
10.9.12 I2C Master Status Control (I2C_MASTER_STAT_CTRL)
Table 10.55 I2C_MASTER_STAT_CTRL 0xF20054
Bit
Field Name
Type
Reset
Value
Comment
15 - 0
EPROM_START_ADDR
R/W
0x0000
EPROM address offset where
I2C Master read operation
should take place
16
START_I2C_EPROM_READ
WO
0b0
Setting this bit to logical one will
initiate the start of an I2C
EPROM read
19 - 17
Reserved
20
I2C_ABORT
WO
0b0
Setting this bit to logical one will
abort any pending I2C master
operation
21
I2C_SUCCESSFUL
RO
0b0
A value of 1 indicates that a
previous Master I2C read oper-
ation is complete and was suc-
cessful
If successful this bit will stay
high until the next sequence is
initiated.
22
I2C_READ_IN_PROGRESS
RO
0b0
0 = I2C read operation is not in
progress
1 = I2C read operation is in
progress
This bit will stay high as long as
the sequence is in progress and
then will go low upon its com-
pletion.
23
I2C_CHKSUM_FAIL
RO
0b0
A value of 1 indicates that the
ckecksum verification of a I2C
read operation failed
Reset on read
24
I2C_32_BIT_WORD_ERR
RO
0b0
A value of 1 indicates that 32
bits of read data was expected
but the operation was termi-
nated prematurely
Reset on read
25
I2C_22_BIT_WORD_ERR
RO
0b0
A value of 1 indicates that 22
bits of read data was expected
but the operation was termi-
nated prematurely
Reset on read
26
I2C_NACK
RO
0b0
A value of 1 indicates that an
expected ack was not received
Reset on read