IDT I2C Interface
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
4 - 2
July 10, 2012
When in this mode, the state of the external ADS signal is ignored. Once the CPS-16/12/8 completes its
configuration sequence (successfully or unsuccessfully), it reverts to Slave mode (where the ADS signal
becomes active).
4.3.2
Commanded Master Mode
The CPS-16/12/8 can be commanded into temporary Master mode using a maintenance write to the I2C
Master Control Register and I2C Master Status Control Register. In this scenario, the device has come out
of reset in Slave mode with the Master mode external signal left floating, or optionally tied to GND. Writing
to START_I2C_EPROM_READ in the I2C Master Status Control Register causes the device to transition
from Slave to temporary Master mode and read the EEPROM from the address specified in the
EPROM_START_ADDR.
Commanded Master mode provides more configuration sequence flexibility. In this scenario the EEPROM
slave address, and the EEPROM start address for the download, are both programmable. Whether or not a
checksum comparison is performed to validate the download is also programmable. These configuration
sequence options are established by writes to the I2C Master Control Register and I2C Master Status
Control Register.
During (and after) the configuration sequence, the CPS-16/12/8 provides status information about the
operation. This status includes whether or not any I
2
C errors occurred, whether the operation is active or
finished, and whether or not the operation was successful. The ability to abort the operation using a
maintenance write to the I2C Master Status Control Register is also provided.
When the device is in temporary Master mode, the state of the external ADS signal is ignored. Once the
device completes its configuration sequence (successfully or unsuccessfully), it reverts to slave mode
(where the ADS signal will become active).
4.3.3
Master Clock Frequency
While in the Master mode, the CPS-16/12/8 can be configured to supply a clock of either 100 kHz (Standard
mode) or 400 kHz (Fast mode).
4.3.4
Register Map
The device’s register map is based on the concept of configuration blocks whose definition and
accompanying data is located at specific places in the EEPROM address map. The definition of the register
map is as follows:
1. Byte addresses 0x0000 and 0x0001 contain the version number to be used as an initial verification of the
registers (see
). Each address must contain the value 0xAA, otherwise the EEPROM contents
will not be loaded.
2. Byte addresses 0x0002 and 0x0003 define the number of configuration blocks that are in the register
map. This value is one less than the number of configuration blocks in the device. For one image, the
value should be 0x00 for each address.
3. Byte address 0x0004 is the start of the first block. All blocks have the same format.
4. The first byte in the block encodes the lower 8 bits [7:0] of a 10-bit word defining the number of registers
represented in this block. A value of 0 = 1 register, 1 = 2 registers, and so on.
5. The first two bits in the second byte (bits 7 and 6) are the upper two bits of the number of registers loaded.
The lower 6 bits are the upper bits of the address (bits [21:16]).
6. Bytes 3 and 4 of the block encode the address to load the data that follows. The 22-bit address is the
24-bit device register address with the lower 2 bits dropped and assumed to be zero.
7. The remainder of the bytes of the block contain the data to be loaded into consecutive register addresses.
8. Subsequent blocks use the same format, number of registers, address, and data.
