IDT CPS Registers
Revision 1.5
Integrated Device Technology, Inc.
CPS-16/12/8 User Manual
10 - 52
July 10, 2012
10.13 QUAD CONTROL REGISTERS
Table 10.81 QUAD_CTRL Control Register Map
10.13.1 Quad 0 Control Register (QUAD_0_CTRL)
Base Address (hex)
Associated Registers
0xFF0000-0xFF0004
QUAD_0_CTRL, QUAD_0_ERROR_REPORT_EN
0xFF1000-0xFF1004
QUAD_1_CTRL, QUAD_1_ERROR_REPORT_EN
0xFF2000-0xFF2004
QUAD_2_CTRL, QUAD_2_ERROR_REPORT_EN
0xFF3000-0xFF3004
QUAD_3_CTRL, QUAD_3_ERROR_REPORT_EN
0xFFF000
Broadcast To All Quads Register
Table 10.82 QUAD_0_CTRL 0xFF0000
Bit
Field Name
Type
Reset
Value
Comment
1 - 0
SPEEDSEL
R/W
0b00
Port Speed Selection. Default is set by
external pins
00 = 1.25 Gbps
01 = 2.5 Gbps
10 = 3.125 Gbps
4 - 2
TCOEFF
R/W
0b000
Transmitter Pre-emphasis
000 = 0%
001 = 6.5%
010 = 13%
011 = 19.5%
100 = 26%
101 = 32.5%
110 = 39%
111 = 45.5%
5
STD_ENH_SEL
R/W
0b1
0 = standard
1 = enhanced
6
FORCE_REINIT
R/W
0b0
1 = Force Reinit
0 = don’t initialize
9 - 7
TXDRVSEL
R/W
0b010
Transmitter Drive Strength
000 = Maximum
010 = Long Haul
100 = Short Haul
111 = Minimum
10
PLL_LANE_0_1_RESET
R/W
0b1
Forces reset of Lanes 0 and 1
0 = Reset
1 = Deassert reset