ICS PCI-WDT 500, Руководство по эксплуатации продукта

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Manual Number: 00650-144-1 Page 27
Appendix A: Programmable Interval Timer
This appendix includes basic information about the type 8254 Counter/Timer chip. For those inter-
ested in more detailed information, a full description can be found in the manufacturer’s data
sheets.
Operation Modes
Modes of operation are described in the following paragraphs to familiarize you with the power
and versatility of this device. The following conventions apply in describing operation of type
8254 chips:
Clock A positive pulse into the counter’s clock input.
Trigger A rising edge input to the counter’s gate input.
Counter Loading Programming a binary count into the counter.
Mode 0: Pulse on Terminal Count
After the counter is loaded, the output is set low and will remain low until the counter decrements
to zero. The output then goes high and remains high until a new count is loaded into the counter. A
trigger enables the counter to start decrementing. This mode is commonly used for event counting
with counter 0.
Mode 1: Retriggerable One-Shot
The output goes low on the clock pulse following a trigger to begin the one-shot pulse and goes
high when the counter reaches zero. Additional triggers result in reloading the count and starting
the cycle over. If a trigger occurs before the counter decrements to zero, a new count is loaded.
Thus, this forms a retriggerable one-shot. In mode 1, a low output pulse is provided with a period
equal to the counter countdown time.
Mode 2: Rate Generator
This mode provides a divide-by-N capability where N is the count loaded into the counter. When
triggered, the counter output goes low for one clock period after N counts, reloads the initial count,
and the cycle starts over. This mode is periodic, the same sequence is repeated indefinitely until the
gate input is brought low. This mode also works well as an alternative to mode 0 for event counting.