ICS PCI-WDT 500, Руководство по эксплуатации продукта

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Manual Number: 00650-144-1 Page 5
Chapter 2: Functional Description
This multifunction card contains a watchdog timer. Additionally, one or more options may be
included on your card. These are: a computer power supply monitor, a computer internal tempera-
ture monitor, an optional capability to read the temperature, a fan-speed monitor, a fan-speed con-
trol, an on-card buzzer to signal watchdog timeout, and a fan-speed control.
Watchdog
It’s a fact of life that computers and programs can fail. If a computer or program fails it can cause
catastrophic damage. Even if a program merely locks up, an unattended computer could be down
for days. There are two methods to reduce risk of computer or software failure: (a) redundancy and
(b) a watchdog circuit. Neither method offers 100% assurance, but both of these methods reduce
risk or consequences of failure. Redundancy, a duplication of computer circuitry, is very expensive.
On the other hand, a watchdog card offers excellent protection from temporary malfunctions at
very low cost.
Your application program must communicate with the watchdog circuit at prescribed intervals. If
this communication (“prompt”) is missed, the watchdog can be programmed to initiate a computer
reset (reboot). If the reboot is successful, operation may be returned to the previous application
program. If the failure was temporary, proper operation is resumed. If, however, the failure is
persistent, the watchdog will continuously reset the computer. The more frequently the watchdog is
prompted (and shorter watchdog time selected), the less time a faulty computer has to cause dam-
age.
The method used by the PCI-WDT50x card to detect loss of computer function is as follows:
A type 82C54 counter/timer is used. This chip contains three 16-bit counters. A number greater
than zero is set into the chip’s counters 0 and 1 by your application program. The watchdog is
armed by software command and both counters begin counting down. As long as the computer is
operating properly, both counters will be periodically reloaded to their original programmed values
by your application program before both counters have counted down to zero.
If your software fails to reload the counters, then both counters continue counting until zero is
reached (timeout). When the counters 0 and 1 reach zero, either the power-good line is held low for
approximately 16 milliseconds (performing a hardware reset) through a relay contact, or external
lines (either relay contacts or a de-bounced opto-isolated switch) are active while a buzzer sounds
(if enabled). When a reset condition occurs, the reset circuit is active until a reset pulse returns
from the system bus or power is cycled to the system.
The clock frequency to Counter 0 is derived from the computer’s clock and is 33_MHZ¸16=
2.08333 MHz. (The period is 0.48 msec.) The output of Counter 0 is used as a clock to Counter 1.
Since each counter can divide by any whole number from 2 to 65,536 (2
16
), the watchdog timeout
period may vary from about 2 microseconds to 2060 seconds.