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4.4 Advanced Chipset Setup
This setup functions are working mostly for Chipset (Intel
440BX). These options are used to change the Chipset‘ s
registers. Please carefully change any default setting, otherwise
the system will run unstably.
Configure SDRAM Timing by SPD >
The
S
erial
P
resence
D
etect is a 2048bits EEPROM which contains of the data of the
chip module, capacity, timing, voltage, etc. The system will
configure the SDRAM timing according to the data in the SPD
when it is set enabled.
SDRAM RAS# to CAS# delay >
to specify the relative delay
between row and column address strobe form SDRAM.
SDRAM RAS# Precharge >
this option specifies the length of
time for Row Address Strobe form SDRAW to precharge.
SDRAM CAS# Latency >
to specify the CAS latency timing
form SDRAM DRAM.
DRAM Integrity Mode >
to choose DRAM Integrity Mode;
ECC/EC
will enable the
E
rror
C
hecking and
C
orrection DRAM
integrity mode.
DRAM Refresh Rate >
to specify the timing for DRAM Refresh
Memory Hole :
to specify the location of a memory hole in the
CMOS RAM. This setting reserves 15MB to 16MB memory
address space for ISA expansion cards that specifically require
this setting. Memory from 15MB and up will be unavailable to
