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Advanced Chipset Features
DRAM Timing By SPD [Disabled] DRAM
Clock [Host CLK]
SDRAM Cycle Length [3]
Bank Interleave [Disabled]
Memory Hole [Disabled]
P2C/C2P Concurrency [Enabled]
System BIOS Cacheable [Disabled]
OnChip USB [Disabled]
USB Keyboard Support [Disabled]
USB Mouse Support [Disabled]
OnChip Sound [Auto]
CPU to PCI Write Buffer [Enabled]
PCI Dynamic Bursting [Enabled]
PCI Master 0 WS Write [Enabled]
PCI Delay transaction [Enabled]
PCI#2 Access #1 Retry [Enabled]
Memory Parity/ECC Check [Disabled]
Item Help
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Menu Level
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Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults
This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external cache.
It also coordinates communications between the conventional ISA bus and
the PCI bus. It must be stated that these items should never need to be
altered. The default settings have been chosen because they provide the
best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost
while using your system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully
chosen and should only be altered if data is being lost. Such a
scenario might well occur if your system had mixed speed DRAM
chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
DRAM Timing By SPD
This item allows you to select the value in this field, depending on whether
the board has paged DRAMs or EDO (extended data output) DRAMs.
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The Choice:
Enabled, Disabled.
DRAM Clock
This item allows you to control the DRAM speed.
The Choice: Host Clock, HCLK-33M, HCLK+33M.
SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
The Choice: 2, 3.
Memory Hole
In order to improve performance, certain space in memory is reserved for
ISA cards. This memory must be mapped into the memory space below
16MB.
The Choice: 15M-16M, Disabled.
P2c/C2P Concurrency
This item allows you to enable/disable the PCI to CPU, CPU to PCI
concurrency.
The choice: Enabled, Disabled.
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result.
The Choice: Enabled, Disabled.
OnChip USB
This should be enabled if your system has a USB installed on the system
board and you want to use it. Even when so equipped, if you add a higher
performance controller, you will need to disable this feature.
The Choice: Enabled, Disabled.
USB Keyboard Support
