ROCKY-3705EV-R2 Socket 370 Celeron
TM
, Pentium III
®
& Tualatin Processor with Ethernet , VGA , Audio Board
45
SDWCLK Control DQM/MD
This item controls the phase of SDWCLK used for DQM/MD signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
EGMRCLK Control
This item controls the phase of EGMRCLK that lags behind SDCLK.
The choice: -1.0ns~+6.5ns (Default 0.0ns)
EGMWCLK Control
This item controls the phase of EGMWCLK that lags ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The choice: Enabled, Disabled.
Vedio RAM Cacheable
Select Enabled allows caching of the video RAM , resulting in better system
performance. However, if any program writes to this memory area, a system
error may result.
The choice: Enabled, Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this
area is reserved, it cannot be cached. The user information of peripherals that
need to use this area of system memory usually discusses their memory
requirements.
The Choice: Enabled, Disabled.
ROCKY-3705EV-R2 Socket 370 Celeron
TM
, Pentium III
®
& Tualatin Processor with Ethernet , VGA , Audio Board
46
AGP Aperture Size
Select the size of Accelerated Graphics Port (AGP) aperture. The aperture is a
portion of the PCI memory address range dedicated for graphics memory
address space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation.
The Choice: 4M, 8M, 16M, 32M, 64M, 128M, 256M.
Graphic Window WR Combin
Use this item to enable or disable CPU support for WR Combin.
The Choice : Enable , Disable .
Concurrent Function ( MEM )
This item is CPU & PCI Masters Concurrently Access Memory Function. Select
enabled allows CPU access memory cycles and PCI masters access memory
cycles concurrently issued onto host bus and PCI bus, respectively, and then the
memory access cycles will be rearranged by SiS630ET to memory sequentially.
The choice: Enabled, Disabled
Concurrent Function ( PCI )
This item is CPU & PCI Masters Concurrently Access PCI Bus Function. Select
enabled allows CPU access PCI bus cycle and PCI masters access memory
cycles concurrently issued onto host bus and PCI bus, respectively.
The choice: Enabled, Disabled.
CPU Pipeline Control
When enabled this item, only one pending cycle is allowed at one time.
When disabled, there might be more than two pending cycles at one time
depends on the CPU behaviour.
The choice: Enabled, Disabled.
