ROCKY-3705EV-R2 Socket 370 Celeron
TM
, Pentium III
®
& Tualatin Processor with Ethernet , VGA , Audio Board
43
Dram Backgroud Command
This item is lead-off time control for DRAM background command. When select
'Delay 1T' , background commands are issued 1 clock behind memory address
(MA) been issued. When select 'Normal', background command and MA are
issued at the same time.
The choice: Delay 1T, Normal.
LD-Off Dram RD/WR Cycles
The item is lead-off time control for DRAM Read/Write Cycles. When select
'Delay 1T' , memory read/write command is issued 1 clock behind memory
address (MA) been issued. When select 'Normal', read/write command amd MA
are issued at the same time.
The choice: Delay 1T, Normal.
Write Recovery Time
This item defines the Data-in to PRE command period.
The choice: 1T, 2T
VCM REF To ACT/REF Delay
This item defines VCM REF to REF/ACT command period.
The choice: 10T, 9T.
VCM ACCT To ACT/REF Delay
This item defines VCM ACT to ACT/REF command period.
The choice: 10T, 9T, 8T, Reserved.
Early CKE Delay 1T Cntrl
When this item is enabled, CKE is driven out from flip-flop. It is used when
system operates under low frequency and CKE delay adjustment method defined
in the 'Early CKE Delay Adjustment' which can not meet setup time and hold time
requirement.
ROCKY-3705EV-R2 Socket 370 Celeron
TM
, Pentium III
®
& Tualatin Processor with Ethernet , VGA , Audio Board
44
The choice: Normal, Delay 1T.
Early CKE Delay Adjust
This item controls the timing for CKE. Various delay options are provided to
ensure that CKE can meet SDRAM setup time and hold time specification when
CKE is driven out.
The Choice: 1ns, 2ns, 3ns, 4ns, 5ns, 6ns, 7ns, 8ns.
Mem Command Output Time
This item is to control the timing to drive memory command onto memory bus.
The choice: Normal, Delay 1T.
SDRAM/VCM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
The Choice: 2, 3 , SPD
SDRCLK Control
This item controls the phase of SDRCLK that lags behind SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control CS#/CKE
This item controls the phase of SDWCLK used for chip set select signals pin that
lags ahead SDCLK.
The choice: Enabled, Disabled.
SDWCLK Control MA/SRAS
This item controls the phase of SDWCLK used for MA/ SRAS signals that lags
ahead SDCLK.
The choice: +5.0ns~-2.5ns (Default 0.0ns)
