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Appendix A Watchdog Timer
The Watchdog Timer is a device to ensure that standalone systems can always
recover from abnormal conditions that cause the system to crash. These
conditions may have resulted from an external EMI or a software bug. When the
system stops working, hardware on the board will perform a hardware reset (cold
boot) to bring the system back to a known state.
Three I/O ports control the operation of Watchdog Timer, which is described in the
following table.
I/O PORT
ACTION DESCRIPTION
443 (hex)
Write
Set time-out period
443 (hex)
Read
Enable the refreshing of the Watchdog Timer.
043/843 (hex) Read
Disable the Watchdog Timer.
Prior to enabling the Watchdog Timer, set the time-out period. The range of the
timer is 1 to 255 sec, set in increments of 1 second. Send the time-out value to the
I/O port 443H, and then enable it by reading data from the same I/O port. This will
activate the timer, which will eventually time out and check and monitor the CPU
board. This must be done within the time-out period that is set by the software.
For additional help, please refer to the example program. Finally, disable the
Watchdog timer by reading the I/O port 843H or 043H, otherwise the system will
reset unconditionally. Please refer to the sample assembly program on the next
page for more details.
Note: A margin of error of at least 5% must be maintained to avoid unknown
routines in the operating system (DOS), such as disk I/O, which can be very
time-consuming. Therefore if the time-out period is set to 10 seconds, the
I/O port 443H must be completely read within 7 seconds.
