IBT Technologies IB500, Руководство пользователя

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BIOS SETUP
42 IB500 User’s Manual
SDRAM Speculative Read
The chipset can "speculate" on a DRAM read address, thus reducing read
latencies. The CPU issues a read request containing the data memory
address. The DRAM controller receives the request. When this field is
Enabled, the controller issues the read command slightly before it has
finished decoding the data address.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
enabled.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
are cached, provided that the cache controller is disabled.
8 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between
PCI-originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus. This field let you add
recovery time (in bus clock cycles) for 8-bit I/O.
16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between
PCI-originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus. This field let you add
recovery time (in bus clock cycles) for 16-bit I/O.
Memory Hole at 15M-16M
In order to improve performance, certain space in memory can be reserved
for ISA cards. This field allows you to reserve 15MB to 16MB memory
address space to ISA expansion cards. This makes memory from 15MB
and up unavailable to the system. Expansion cards can only access
memory up to 16MB. By default, this field is set to
Disabled.
PCI 2.1 Compliance
Concurrent PCI allows multiple PCI transfers from the PCI master buses
to memory to CPU. By default, this field is set to
Disabled .