IBT Technologies IB500, Руководство пользователя

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BIOS SETUP
40 IB500 User’s Manual
Chipset Features Setup
This Setup menu controls the configuration of the CPU card chipset.
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
Auto Configuration
:
Enabled PCI 2.1 Compliance : Disabled
DRAM Timing : 60ns DRAM Refresh Rate : 15.6
µ
s
DRAM Leadoff Timing
:
10/6/4 CPU Warning Temperature : Disabled
DRAM Read Burst (EDO/FP) : X333/x444 Current System Temp. : 37
°
C/98
°
F
DRAM Write Burst Timing
:
X333 Current CPU Temperature : 25
°
C/77
°
F
Fast EDO Lead Off : Enabled Current CPU Fan Speed : 5720 RPM
Refresh RAS# Assertion
:
4 Clks Current Chassis Fan Speed : 5443 RPM
Fast RAS to CAS Delay : 3
DRAM Page Idle Timer
:
2 Clks Vio (V) : 1.98 V Vcore (V) : 1.50 V
DRAM Enhanced Paging : Disabled Vio (V) : 1.98 V Vcore (V) : 1.50 V
Fast MA to RAS# Delay
:
2 Clks +12 V : 12.46 V +5V : 5.10 V
SDRAM (CAS Lat/RAS-to-CAS) : 3/3 -5V : - 5.21 V -12 V : -12.54V
SDRAM Speculative Read : Disabled
System BIOS Cacheable : Disabled ESC : Quit
á â à ß
: Select
Item
Video BIOS Cacheable : Disabled F1 : Help PU/PD/+/- : Modify
8 Bit I/O Recovery Time : 3 F5 : Old Values (Shift) F2 : Color
16 Bit I/O Recovery Time : 2 F6 : Load BIOS Defaults
Memory Hole At 15M-16M : Disabled F7 : Load Setup Defaults
Auto Configuration
Auto Configuration selects predetermined optimal values for chipset
parameters. When
Disabled , chipset parameters revert to setup
information stored in CMOS. Many fields in this screen are not available
when Auto Configuration is
Enabled .
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
DRAM Leadoff Timing
Select the combination of CPU clocks the DRAM on the IB500 requires
before each read from or write to the memory. Changing the value from
the setting determined by the board designer for the installed DRAM may
cause memory errors.
DRAM Read Burst (EDO/FP)
Set the timing for burst-mode reads from DRAM. The lower the timing
numbers, the faster the system addresses memory. Selecting timing
numbers lower than the installed DRAM is able to support can result in
memory errors.