IBT Technologies IB500, Руководство пользователя

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BIOS SETUP
IB500 User’s Manual 41
DRAM Write Burst Timing
Set the timing for burst-mode writes from DRAM. The lower the timing
numbers, the faster the system addresses memory. Selecting timing
numbers lower than the installed DRAM is able to support can result in
memory errors.
Fast EDO Leadoff
Select Enabled only for EDO DRAMs in either a synchronous cache or a
cacheless system. It causes a 1-HCLK pull-in for all read leadoff latencies
for EDO DRAMs (i.e., page hits, page misses, and row misses). Select
Disabled if any of the DRAM rows are populated with FPM DRAMs.
Refresh RAS# Assertion
Select the number of clock ticks RAS# is asserted for refresh cycles.
Fast RAS To CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the
transition from RAS to Column Address Strobe (CAS).
DRAM Page Idle Timer
Select the amount of time in HCLKs that the DRAM controller waits to
close a DRAM page after the CPU becomes idle.
DRAM Enhanced Paging
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower.
Fast MA to RAS# Delay
The values in this field are set by the system board designer, depending on
the DRAM installed. Do not change the values in this field unless you
change specifications of the installed DRAM or the installed CPU.
SDRAM(CAS Lat/RAS-to-CAS)
You can select a combination of CAS latency and RAS-to-CAS delay in
HCLKs of 2/2 or 3/3. The system board designer should set the values in
this field, depending on the DRAM installed. Do not change the values in
this field unless you change specifications of the installed DRAM or the
installed CPU.