IBM Power 595, Технический обзор и введение

Страница: 90 / 188

78
IBM Power 595 Technical Overview and Introduction
2.7 Memory subsystem
The Power 595 server uses fully buffered, Double Data Rate (DDR2) DRAM memory DIMMs.
The DIMM modules are X8 organized (8 data bits per module). Support is provided for
migrated X4 DIMM modules. Memory DIMMs are available in the following capacities: 1 GB, 2
GB, 4 GB, 8 GB, and 16 GB. Each orderable memory feature (memory unit) provides four
DIMMs.
The memory subsystem provides the following levels of reliability, availability, and
serviceability (RAS):
ECC, single-bit correction, double-bit detection
Chip kill correction
Dynamic bit steering
Memory scrubbing
Page deallocation (AIX only)
Dynamic I/O bit line repair for bit line between the memory controller and synchronous
memory interface chip (SMI) and between SMI chips. The SMI chips connect the memory
controllers to memory DIMMs.
ECC on DRAM addressing provided by SMI chip
Service processor interface
Each of the four dual-core POWER6 processors within a processor book has two memory
controllers as shown in Figure 2-32 on page 79. Each memory controller is connected to a
memory unit. The memory controllers use an elastic interface to the memory DIMMs that runs
at four times the memory speed.
Note: One memory unit for each POWER6 processor must be populated at initial order
(four units per installed processor book).