IBM Power 595, Технический обзор и введение

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Chapter 4. Continuous availability and manageability
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bit line, it can dynamically steer the data stored at this bit line into
one of a number of spare lines.
Figure 4-4 shows memory protection capabilities in action.
Figure 4-4 Memory protection capabilities in action
Memory page deallocation
Although coincident single cell errors in separate memory chips is a statistic rarity, POWER6
processor systems can contain these errors by using a memory page deallocation scheme for
partitions running AIX and for memory pages owned by the POWER Hypervisor. If a memory
address experiences an uncorrectable or repeated correctable single cell error, the service
processor sends the memory page address to the POWER Hypervisor to be marked for
deallocation.
The operating system performs memory page deallocation without any user intervention and
is transparent to end users and applications.
The POWER Hypervisor maintains a list of pages marked for deallocation during the current
platform IPL. During a partition IPL, the partition receives a list of all the bad pages in its
address space.
In addition, if memory is dynamically added to a partition (through a Dynamic LPAR
operation), the POWER Hypervisor warns the operating system if memory pages are
included that must be deallocated.
Finally, if an uncorrectable error occurs, the system can deallocate the memory group
associated with the error on all subsequent system reboots until the memory is s intended to
guard against future uncorrectable errors while waiting for parts replacement.
Memory control hierarchy
While POWER6 processor systems maintain the same basic function as POWER5, including
chipkill detection and correction, a redundant bit steering capability, and OS based memory
page deallocation, the memory subsystem is structured differently.
The POWER6 chip includes two memory controllers (each with four ports) and two L3 cache
controllers. Delivering exceptional performance for a wide variety of workloads, the Power 595
uses both POWER6 memory controllers and both L3 cache controllers for high memory
Note: Although memory page deallocation handles single cell failures, because of the
sheer size of data in a data bit line, it might be inadequate for dealing with more
catastrophic failures. Redundant bit steering continues to be the preferred method for
dealing with these types of problems.