Chapter 2. Architectural and technical overview
71
Figure 2-28 IBM Power 595 processor book architecture
The available processor books are listed in Table 2-12.
Table 2-12 Available processor books
Feature code
Description
#4694
0/8-core POWER6 4.2 GHz CoD 0-core Active Processor Book
MCM T
POWER6
dual core
L3
16 MB
SEEPROM
512 KB
SEEPROM
512 KB
L3
16 MB
8 byte write
8 byte read
16 bit cmd/addr
8 byte write
8 byte read
16 bit cmd/addr
I2C
I2C
Mem Ctrl 0
Me
m Ct
rl 1
L3 Di
r
& Ct
rl
2
L3
D
ir
& C
tr
l 1
MCM S
POWER6
dual core
L3
16 MB
SEEPROM
512 KB
SEEPROM
512 KB
L3
16 MB
8 byte write
8 byte read
16 bit cmd/addr
8 byte write
8 byte read
16 bit cmd/addr
I2C
I2C
Mem
Ct
rl 0
Me
m C
trl
1
L3
Di
r
& Ct
rl
2
L3 Di
r
& Ctr
l 1
MCM U
POWER6
dual core
L3
16 MB
SEEPROM
512 KB
SEEPROM
512 KB
L3
16 MB
8 byte write
8 byte read
16 bit cmd/addr
8 byte write
8 byte read
16 bit cmd/addr
I2C
I2C
Me
m Ct
rl 0
Mem
Ct
rl
1
fu
ll b
frd
D
IM
M
ful
l b
frd
D
IMM
fu
ll b
frd
D
IM
M
fu
ll b
frd
D
IM
M
fu
ll b
frd
D
IM
M
fu
ll b
frd
D
IM
M
fu
ll b
frd
DI
M
M
ful
l bfr
d D
IMM
GX Adapter
fu
ll b
frd
D
IM
M
ful
l bf
rd
D
IM
M
fu
ll b
frd
DI
M
M
ful
l bf
rd
D
IM
M
fu
ll b
frd
DI
M
M
ful
l b
frd
D
IM
M
fu
ll b
frd
DI
M
M
fu
ll b
frd
D
IMM
GX Adapter
GX Adapter
4 byte read (53 bits total)
4 byte write (53 bits total)
GX+/GX++/GX' BUS
MCM V
POWER6
dual core
L3
16 MB
SEEPROM
512 KB
GX Adapter
fu
ll b
fr
d
D
IM
M
fu
ll b
fr
d
DI
M
M
fu
ll b
fr
d
D
IM
M
ful
l bfr
d D
IMM
fu
ll b
fr
d
D
IM
M
ful
l bfr
d D
IMM
fu
ll b
fr
d
D
IM
M
ful
l bf
rd
D
IM
M
SEEPROM
512 KB
L3
16 MB
1 byte write
2 byte read
16 byte write
16 byte read
30 bit addr
16 byte write
16 byte read
30 bit addr
I2C
I2C
Me
m
C
tr
l 0
Me
m Ct
rl
1
GX+/GX++/GX' BUS
EI3
EI3
1 byte write (X4)
2 byte read (X4)
EI3
EI3
fu
ll b
fr
d
D
IM
M
ful
l bf
rd
D
IM
M
fu
ll b
fr
d
D
IM
M
fu
ll b
fr
d
DI
M
M
fu
ll b
fr
d
D
IM
M
fu
ll b
fr
d
D
IM
M
fu
ll b
fr
d
D
IM
M
ful
l bfr
d
D
IMM
P0
P1
P2
P3
P0
P1
P2
P3
EI3
EI3
P0
P1
P2
P3
P0
P1
P2
P3
EI3
EI3
P0
P1
P2
P3
P0
P1
P2
P3
MCM to MCM
intra-node
pnt to pnt
Fabric Busses.
8 bytes each
direction (180
bits) (x3)
1 byte write (X4)
2 byte read (X4)
Inter-node
Fabric Busses 8
bytes each direction
(180 bits) (X8)
Node Controller
(SP)
Node Controller
(SP)
FSI fanout
FSI fanout
L3 Di
r
& C
tr
l 2
L3
D
ir
& C
tr
l 1
L3
Di
r
& Ct
rl
2
L3
D
ir
& C
trl 1
Interplane
Slot
Inter-node
Fabric Busses
32 Double or Single High DIMM sites
4 byte write (53 bits total)
4 byte read (53 bits total)
4 MB
L2
VPD /SVPD
card
10/100 Ethernet to Cage Controllers
49 bits
(X4)
106 bits
106 bits
49 bits
(X4)
8 bytes each direction (180 bits)
4 MB
L2
4 MB
L2
4 MB
L2
4 MB
L2
4 MB
L2
4 MB
L2
4 MB
L2
Содержание Power 595
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