IBM Power 595, Технический обзор и введение

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Chapter 2. Architectural and technical overview
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Figure 2-32 Memory system logical view
Each processor book supports a total of eight memory units (32 DIMMS or eight memory
features). A fully configured Power 595 server with eight processor books supports up to 64
memory units (256 DIMMs). Using memory features that are based on 64 GB DIMMs, the
resulting maximum memory configuration is four TB.
2.7.1 Memory bandwidth
The Power 595 memory subsystem consists of L1, L2, and L3 caches along with the main
memory. The bandwidths for these memory components is shown in Table 2-14
Table 2-14 Memory bandwidth
Note: One memory unit is equal to an orderable memory feature. One memory unit
contains four memory DIMMs.
Description Bus size Bandwidth
L1 (data) 2 x 8 bytes 80 GBps
L2 2 x 32 bytes 160 GBps
L3 4 x 8 bytes 80 GBps (per 2-core MCM)
2.56 TBps (per 64-core system)
Main memory 4 x 1 byte (write)
4 x 2 bytes (read) 42.7 GBps (per 2-core MCM)
1.33 TBps (per 64-core system)