Hyundai HPT-4205, Руководство по обслуживанию

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Plasma TV Service Manual 14/03/2005
EXMCLR P3 I/pd external mode clear (with internal pull-down)
LLC P4 O line-locked system clock output (27 MHz nominal)
RES P5 O reset output (active LOW)
ADP8 P6 O MSB of direct analog-to-digital converted output data (VSB)
ADP4 P7 O MSB - 4 of direct analog-to-digital converted output data
(VSB)
ADP1 P8 O MSB - 7 of direct analog-to-digital converted output data
(VSB)
INT_A P9 O/od I
2
C-bus interrupt flag (LOW if any enabled status bit has
changed)
SDA P10 I/O/od serial data input/output (I 2 C-bus)
AMCLK P11 O audio master clock output, up to 50% of crystal clock
ALRCLK P12 O/st/pd audio left/right clock output; can be strapped to supply via a
3.3 kW resistor to indicate
that the default 24.576 MHz crystal (ALRCLK = 0; internal
pull-down) has been replaced
by a 32.110 MHz crystal (ALRCLK = 1); see notes 5 and 7
TEST19 P13 I/pu do not connect, reserved for future extensions and for testing:
scan input
Notes
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od
= open-drain.
2. In accordance with the
“ IEEE1149.1 ” standard the pads TDI, TMS, TCK and TRST are input pads
with an internal pull-up transistor and TDO is a 3-state output pad.
3. For board design without boundary scan implementation connect the TRST pin to ground.
4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to
force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at
once.
5. Pin strapping is done by connecting the pin to the supply via a 3.3
resistor. During the power-up
reset sequence the corresponding pins are switched to input mode to read the strapping level. For the
default setting no strapping
resistor is necessary (internal pull-down).
6. Pin RTCO operates as I 2 C-bus slave address pin; RTCO = 0 slave address 42H/43H (default);
RTCO = 1 slave address 40H/41H.
7. Pin ALRCLK: 0 = 24.576 MHz crystal (default; Philips order number 4322 143 05291); 1 = 32.110
MHz crystal
12.23. TPS72501
12.23.1. General Description
The TPS725xx family of 1-A low-dropout (LDO) linear regulators has fixed voltage options available that
are commonly used to power the latest DSPs, FPGAs, and microcontrollers. An adjustable option
ranging from 1.22 V to 5.5 V is also available. The integrated supervisory circuitry provides an active
low RESET signal when the output falls out of regulation. The no capacitor/any capacitor feature allows
the customer to tailor output transient performance as needed. Therefore, compared to other regulators
capable of providing the same output current, this family of regulators can provide a stand alone power
supply solution or a post regulator for a switch mode power supply.
These regulators are ideal for higher current applications. The family operates over a wide range of
input voltages (1.8 V to 6 V) and has very low dropout (170 mV at 1-A).
Ground current is typically 210 µA at full load and drops to less than 80 µA at no load. Standby current
is less than 1 µA.