Hyundai HPT-4205, Руководство по обслуживанию

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Plasma TV Service Manual 14/03/2005
12.19. TDA1308
12.19.1. General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for
portable digital audio applications. It gets its input from two analogue audio outputs (DACA_L and
DACA_R) of MSP 34x0G. The gain of the output is adjustable by the feedback resistor between the
inputs and outputs.
12.19.2. Features
•
Wide temperature range
•
No switch ON/OFF clicks
•
Excellent power supply ripple rejection
• Low power consumption
•
Short-circuit resistant
•
High performance
• H
igh signal-to-noise ratio
•
High slew rate
•
Low distortion
•
Large output voltage swing.
12.19.3. Pinning
SYMBOL PIN DESCRIPTION
OUTA 1 Output A
INA(neg) 2 Inverting input A
INA(pos) 3 Non-inverting input A
V
SS
4 Negative supply
INB(pos) 5 Non-inverting input B
INB(neg) 6 Inverting input B
OUTB 7 Output B
V
DD
8 Positive supply
12.20. PI5V330
12.20.1. General Description
The PI5V330 is well suited for video applications when switching composite or RGB analogue. A
picture-in-picture application will be described in this brief. The pixel-rate creates video overlays so two
or more pictures can be viewed at the same time. An inexpensive NTSC titler can be implemented by
superimposing the output of a character generator on a standard composite video background.
12.21. AD9883A
12.21.1. General Description
The AD9883A is a complete 8-bit, 140 MSPS, monolithic analog interface optimized for capturing RGB
graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and
full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync
and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883A
’ s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output
frequencies range from 12 MHz to140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When
the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A
sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are
maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green
applications. A clamp signal is generated internally or may be provided by the user through the CLAMP
input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP
surface-mount plastic package and is specified over the
– 40.  C to +85.  C temperature range.