Hyundai HPT-4205, Руководство по обслуживанию

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Plasma TV Service Manual 14/03/2005
SCL
A0 Serial Port Data Clock (100 kHz Maximum)
Serial Port Address Input 1 3.3 V CMOS
3.3 V CMOS 56
55
Pin Function Descriptions:
Pin Name Function
OUTPUTS
HSOUT
VSOUT
SOGOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity
and duration of this output can be programmed via serial bus registers. By
maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.
Vertical Sync Output
A reconstructed and phase-aligned version of the video Vsync. The polarity of this
output can be controlled via a serial bus bit. The placement and duration in all
modes is set by the graphics transmitter.
Sync-On-Green Slicer Output
This pin outputs either the signal from the Sync-on-Green slicer comparator or an
unprocessed but delayed version of the Hsync input. See the Sync Processing
Block Diagram (Figure 12) to view how this pin is connected. (Note: Besides slicing
off SOG, the output from this pin gets no other additional processing on the
AD9883A. Vsync separation is performed via the sync separator.)
SERIAL PORT (2-WIRE)
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the 2-
Wire Serial Control Port section.
DATA OUTPUTS
RED
GREEN
BLUE
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to
output is fixed. When the sampling time is changed by adjusting the PHASE
register, the output timing is shifted as well. The DATACK and HSOUT outputs are
also moved, so the timing relationship among the signals is maintained. For exact
timing information, refer to Figures 7, 8, and 9.
DATA CLOCK OUTPUT
DATACK
Data Output Clock
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. It is produced by the internal clock generator and is synchronous
with the internal pixel sampling clock. When the sampling time is changed by
adjusting the PHASE register, the output timing is shifted as well. The Data,
DATACK, and HSOUT outputs are all moved, so the timing relationship among the
signals is maintained.
INPUTS
RAIN
GAIN
BAIN
HSYNC
VSYNC
Analog Input for Red Channel
Analog Input for Green Channel
Analog Input for Blue Channel
High impedance inputs that accept the Red, Green, and Blue channel graphics
signals, respectively. (The three channels are identical, and can be used for any
colors, but colors are assigned for convenient reference.) They accommodate
input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to
these pins to support clamp operation.
Horizontal Sync Input
This input receives a logic signal that establishes the horizontal timing reference
and provides the frequency reference for pixel clock generation. The logic sense of
this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only the leading
edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise immunity, with a nominal input
threshold of 1.5 V.
Vertical Sync Input