TC-265/365 SERVICE MANUAL
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Title
Number
Revision
Size
B
Date:
5-Dec-2003
Sheet of
File:
D:\RPV599A V2.0\material\af(Fig3)1.DDB Drawn By:
FM IF IC
IF AMP
DET
DET
HPF AMP
AF
AF AMP
HPF
MUTE SW
AF PF AMP
AFCO SW SP
AFCO SW
LPF
1
37
42
2
BUSY
MUTE
AFCO
TI
MPU
QT/DQT
LPF
W/N SW
Fig. 3. AF amplifier and squelch
6) Receiving signaling
CTCSS/CDCSS
MCU output signal is filtered by 300Hz low-pass filter and the filtered signal is input to the
microprocessor. MCU determines whether the CTCSS or CDCSS matches the preset value, and
controls the MUTE and AFCO and the speaker sounds output according to the squelch results.
2-Tone/5-Tone
IF processing IC output signal is filtered by IC9
（
TC-265
）
/IC14
（
TC-365
）
and then applied to the
microprocessor. MCU compares TTS with the preset value and controls MUTE and AFCO and
speaker output according to squelch results.
3. PLL frequency synthesizer
PLL circuit generates the first local oscillator signal for receive and the RF signal for transmission.
1) PLL
The frequency step of the PLL circuit is 2.5 or 6.25 KHz. A 12.8MHz reference oscillator signal is
divided at PLL by a mixed counter to produce 2.5 or 6.25 KHz reference frequency. The voltage
controlled oscillator (VCO) output signal is buffer amplified, and then divided in PLL by a dual-module
programmable counter. The divided signal is compared in phase with the 2.5 or 6.25 KHz reference
signal in the phase comparator in PLL. The output signal from the phase comparator is filtered
through a low-pass filter and passed to the VCO to control the oscillator frequency. (See Fig. 4)
