HUAWEI ME309-562 eMTC LGA Module
Hardware Guide
Table 3-1
Definitions of pins on the LGA interface
Pin
No.
Pin Name
Pad
Type
Description
Parameter
Min.
(V)
Typ.
(V)
Max.
(V)
Comments
A8
UART0_TX
O
UART0 transmit
output
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
A7
UART0_RX
I
UART0 receive
data input
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
B7
UART0_CTS
I
UART0 clear to
send
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
B8
UART0_RTS
O
UART0 ready
for
receive
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
C7
UART0_DTR
I
Data terminal
ready
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
C6
UART0_DSR
O
UART0 data set
ready
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
B6
UART0_DCD
O
UART0 data
carrier detect
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
A6
UART0_RING
O
UART0 ring
indicator
V
OH
1.44
1.8
1.8
Use as
wake_up out
V
OL
0
-
0.36
A4
UART1_TX
O
UART1 transmit
output
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
A5
UART1_RX
I
UART1 receive
data input
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
B4
UART1_CTS
I
UART1 clear to
send
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
B5
UART1_RTS
O
UART1 ready
for
receive
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
F3
UART2_TX
O
UART2 transmit
output
V
OH
1.44
1.8
1.8
-
V
OL
0
-
0.36
-
F1
UART2_RX
I
UART2 receive
data input
V
IH
1.26
1.8
1.8
-
V
IL
0
-
0.54
-
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