20
The
DMS
option simulates the installation of the 12976B (1000 M-Series) or 13307B (1000 E/F-Series) Dynamic
Mapping System firmware ROMs, providing 38 instructions that control the 12731A Memory Expansion Module to
expand the basic 32K-word logical address space to a 1024K-word physical space.
The
FFP
option simulates the installation of the 12907A (2100), 12977B (1000 M-Series), or 13306B (1000 E-
Series) Fast FORTRAN Processor firmware ROMs, providing several frequently used FORTRAN operations and
extended-precision (three-word) floating-point instructions.
The
DBI
option simulates the installation of the 93585A Double Integer Instructions firmware ROMs. A product of
the HP “specials group,” the microcode added twelve 32-bit integer instructions to the 1000 E-Series repertoire.
DBI instructions are standard equipment on the 1000 F-Series CPU.
The
EMA
option simulates the installation of the 92067A Extended Memory Area firmware ROMs. The RTE-IV
operating system introduced the EMA instructions. EMA provided a mapped data area up to one megaword in
size. These three instructions accelerated data accesses to variables stored in EMA partitions.
The
VMAOS
option simulates the installation of the 92084A Virtual Memory and Operating System firmware ROMs.
The RTE-6/VM operating system introduced Virtual Memory Area (VMA) instructions — a superset of the RTE-IV
EMA instructions — and a set of OS instructions that accelerate certain time-consuming internal operations.
The VMA/OS firmware cannot be installed on a 1000 M-Series; RTE-6/VM will automatically use software
replacements on this machine. The firmware must be installed when running on 1000 E/F-Series hardware; if it is
not, the firmware self-test instruction will fail, and RTE will halt with T = 102021. Under simulation, however, it is
possible to configure the self-test instruction to use the software simulations on an E/F-Series. Entering the
command
SET CPU DEBUG=NOOS
will return a firmware revision code of 0 to RTE, which will permit the use of
the software replacements.
The
VIS
option simulates the installation of the 12824A (for RTE-IVB) or 12829A (for RTE-6/VM) Vector Instruction
Set ROMs, providing vector arithmetic instructions using single- and double-precision values. Vectors may reside
either in EMA/VMA or in regular memory.
The
SIGNAL
option simulates the installation of the 92835A SIGNAL/1000 firmware ROMs. These instructions
provide fast Fourier transforms and complex arithmetic. They use the F-Series floating-point processor and the
Vector Instruction Set.
The 2100 and 1000 CPUs support user microprogramming. Under simulation, execution on these machines of all
instructions in the octal ranges 101400-101777 (2100 and 1000) and 105000-105777 (1000 only) that are not
allocated to installed firmware options will be dispatched to a user-alterable module to aid in the implementation of
user-written microcode simulations. In the absence of such simulations, execution will cause unimplemented
instruction stops. See the comments in the
hp2100_cpu0.c
source file for details.
The 2114, 2115, 2116, and 2100 models support a protected area of memory containing an initial binary loader.
The loader always resides in the highest 64 memory locations, regardless of capacity. Entering the
SET CPU
LOADERENABLE
command makes this area available. Entering the
SET CPU LOADERDISABLE
command
renders this area non-existent, so that reads from the area return zero, and writes to the area are ignored. The
Basic Binary Loader (BBL), configured for the select code of the paper tape reader, initially resides in this area
when the simulator is started. The
LOAD
command may be used with an appropriate absolute binary file to install
a different loader, such as the Basic Binary Disc Loader (BBDL) or Basic Moving-head Disc Loader (BMDL).
Entering the
RESET –P CPU
command will restore the BBL to protected memory.
When enabled by a
SET CPU IDLE
command, execution of the idle loop instructions within the DOS and RTE
operating systems will idle the simulator. While idle, the simulator does not use any host system processor time.
Idle detection is operating-system specific and is disabled by default. When disabled, the simulator will use 100%
of the host-processor CPU time while executing simulated instructions.
Instruction execution trace behavior changes when idling is enabled. See the
Tracing
section below for details.
